Abstract: An embodiment of a technique to determine an expected occurrence of a signal is disclosed. The technique includes receiving first and second signals, and storing delay information representing an expected time delay from an occurrence of the first signal to a point in time corresponding approximately to an expected occurrence of the second signal. The technique further includes responding to an occurrence of the first signal by: waiting for a time interval equivalent to the expected time delay, evaluating the second signal at approximately the end of the time interval, and adjusting the stored delay information if the second signal occurred outside a time window associated with the end of the time interval.

Abstract: A technique is provided for memory control in a device having programmable circuitry, including providing a dedicated memory controller circuit in the device before the programmable circuitry is field programmed. Another technique involves fabricating a device, where the fabricating involves forming programmable circuitry that includes a dedicated memory controller circuit before the circuitry is field programmed.

Abstract: A method of calibrating memory controller signals within an integrated circuit (IC) can include determining an internal delay of a clock network of the IC and generating a calibrated clock signal by applying a first delay to an uncalibrated clock signal, wherein the first delay is determined by subtracting the internal delay of the clock network of the IC from a bitperiod of the uncalibrated clock signal. The method can include determining a classification of at least one data signal according to timing of positive and negative edges of the at least one data signal in comparison with edges of the calibrated clock signal and aligning at least one of positive or negative edges of the at least one data signal to occur at midpoints between edges of the calibrated clock signal according to the classification of the at least one data signal.

Abstract: Within an integrated circuit comprising a memory controller, a method can include, responsive to determining that the memory controller is performing a refresh operation, calculating a new tap setting according to a new maximum value and an old tap setting of the delay circuit. The new maximum value specifies a number of taps of the delay circuit that approximates a predetermined time span. The method can include dynamically adjusting a delay applied to a signal by a delay circuit according to the new tap setting. The delay circuit generates a delayed signal that is provided to the memory controller.

Abstract: A circuit testing approach involves the generation of boundary scan information using test vectors to identify characteristics of a circuit design and a boundary scan implementation therefor. According to an example embodiment of the present invention, test vectors are used in simulation to identify circuit design characteristics for establishing a boundary scan test program. The test vectors are generated using a netlist of the circuit design. The test vectors are used to simulate operation of the circuit, and responses to the simulation are detected and used to identify design-specific circuit characteristics and a boundary scan test program is generated using the design-specific circuit characteristics.