Patents by Inventor Mikhail Grinchuk
Mikhail Grinchuk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11269786Abstract: Systems, apparatus, and/or methods to provide memory data protection. In one example, authenticated encryption may be enhanced via a modification to an authentication code that is associated with encrypted data. The authentication code may be modified, for example, with a nonce value generated for a particular write to memory Decrypted data, generated from the encrypted data, may then be validated based on a modified authentication code. Moreover, data freshness control for data stored in the memory may be provided based on iterative authentication and re-encryption. In addition, a counter used to provide a nonce value may be managed to reduce a size of the counter and/or a growth of the counter.Type: GrantFiled: July 25, 2018Date of Patent: March 8, 2022Assignee: Intel CorporationInventors: Anatoli Bolotov, Mikhail Grinchuk, David M. Durham, Patrick Fleming
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Publication number: 20210312045Abstract: An apparatus to facilitate mitigation of side-channel attacks in a computer system platform is disclosed. The apparatus comprises a cryptographic circuitry, including a plurality of crypto functional units (CFUs) to perform cryptographic algorithms; and jammer circuitry to generate noise to protect the plurality of CFUs from side-channel attacks.Type: ApplicationFiled: June 22, 2021Publication date: October 7, 2021Applicant: Intel CorporationInventors: Anatoli Bolotov, Mikhail Grinchuk, Oleg Rodionov
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Patent number: 10846437Abstract: System and techniques for compressed integrity check counters in memory are described herein. A set of counters may be maintained for data areas in memory. A respective counter is the set of counters is used to provide a variance to encryption operations on a corresponding data area. The respective counter is each time data is modified in the corresponding data area. The respective counter implemented by a generalized multi-dimensional counter (GMDC). In response to a trigger, a counter reset is performed on the set of counters. The counter reset may include refreshing the corresponding data area using a new key and resetting the respective counter to a default value in response to the refresh.Type: GrantFiled: June 28, 2018Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Anatoli Bolotov, Mikhail Grinchuk
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Patent number: 10725861Abstract: System and techniques for error correction code (ECC) memory security are described herein. A write request that includes data is received. An integrity check value (ICV) is computed for the data. Then, the write request is performed, including writing a representation of the data to a data area in memory and writing the ICV into an ECC area in memory. Here, the data area is addressable by a host and the ECC area corresponds to the data area via hardware of the memory.Type: GrantFiled: June 28, 2018Date of Patent: July 28, 2020Assignee: Intel CorporationInventors: Anatoli Bolotov, Mikhail Grinchuk, Rajat Agarwal
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Publication number: 20190050347Abstract: Systems, apparatus, and/or methods to provide memory data protection. In one example, authenticated encryption may be enhanced via a modification to an authentication code that is associated with encrypted data. The authentication code may be modified, for example, with a nonce value generated for a particular write to memory Decrypted data, generated from the encrypted data, may then be validated based on a modified authentication code. Moreover, data freshness control for data stored in the memory may be provided based on iterative authentication and re-encryption. In addition, a counter used to provide a nonce value may be managed to reduce a size of the counter and/or a growth of the counter.Type: ApplicationFiled: July 25, 2018Publication date: February 14, 2019Applicant: Intel CorporationInventors: Anatoli Bolotov, Mikhail Grinchuk, David M. Durham, Patrick Fleming
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Publication number: 20190042795Abstract: System and techniques for compressed integrity check counters in memory are described herein. A set of counters may be maintained for data areas in memory. A respective counter in the set of counters is used to provide a variance to encryption operations on a corresponding data area. The respective counter is each time data is modified in the corresponding data area. The respective counter implemented by a generalized multi-dimensional counter (GMDC). In response to a trigger, a counter reset is performed on the set of counters. The counter reset may include refreshing the corresponding data area using a new key and resetting the respective counter to a default value in response to the refresh.Type: ApplicationFiled: June 28, 2018Publication date: February 7, 2019Inventors: Anatoli Bolotov, Mikhail Grinchuk
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Patent number: 9177251Abstract: Disclosed is a method and apparatus for matching regular expressions. A buffer of symbols giving a number of the last occurrence positions of each symbol is maintained. When two constants match on either side of a regular expression operator, the buffer of symbols is queried to determine if a member of the complement of the regular expression operator occurred between the two constants. If so, then the operator was not satisfied. If not, then the operator was satisfied.Type: GrantFiled: January 16, 2014Date of Patent: November 3, 2015Assignee: Intel CorporationInventors: Alexander Podkolzin, Lav Ivanovic, Anatoli Bolotov, Mikhail Grinchuk, Sergey Afonin
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Publication number: 20140136465Abstract: Disclosed is a method and apparatus for matching regular expressions. A buffer of symbols giving a number of the last occurrence positions of each symbol is maintained. When two constants match on either side of a regular expression operator, the buffer of symbols is queried to determine if a member of the complement of the regular expression operator occurred between the two constants. If so, then the operator was not satisfied. If not, then the operator was satisfied.Type: ApplicationFiled: January 16, 2014Publication date: May 15, 2014Applicant: LSI CORPORATIONInventors: Alexander Podkolzin, Lav Ivanovic, Anatoli Bolotov, Mikhail Grinchuk, Sergey Afonin
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Patent number: 8654969Abstract: Disclosed is a cipher independent cryptographic hardware service. Cipher independent transactions are received into input slots (202). The input slots contain FIFOs to hold the transactions. The transactions are converted from cipher independent form to cipher dependent form (206) and timing as they are removed from the FIFOs. After cryptographic processing by cipher specific hardware, the results are sent to output FIFOs (212). Multiple FIFOs and cryptographic hardware may be used so that multiple cryptographic functions may be performed in parallel and simultaneously.Type: GrantFiled: April 10, 2009Date of Patent: February 18, 2014Assignee: LSI CorporationInventors: Anatoli Bolotov, Mikhail Grinchuk, Lav Ivanovic, Christine E. Severns-Williams
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Patent number: 8650146Abstract: Disclosed is a method and apparatus for matching regular expressions. A buffer of symbols giving a number of the last occurrence positions of each symbol is maintained. When two constants match on either side of a regular expression operator, the buffer of symbols is queried to determine if a member of the complement of the regular expression operator occurred between the two constants. If so, then the operator was not satisfied. If not, then the operator was satisfied.Type: GrantFiled: June 24, 2010Date of Patent: February 11, 2014Assignee: LSI CorporationInventors: Alexander Podkolzin, Lav Ivanovic, Anatoli Bolotov, Mikhail Grinchuk, Sergey Afonin
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Patent number: 8411853Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate second Galois Field elements by performing a first Galois Field inversion on first Galois Field elements, the first Galois Field inversion being different from a second Galois Field inversion defined by an Advanced Encryption Standard and (ii) generate third Galois Field elements by multiplying the second Galois Field elements by an inverse of a predetermined matrix. The second circuit may be configured to (i) generate fourth Galois Field elements by processing the third Galois Field elements in a current encryption round while in a non-skip mode, (ii) generate fifth Galois Field elements by multiplying the fourth Galois Field elements by the predetermined matrix and (iii) present the fifth Galois Field elements as updated versions of the first Galois Field elements in advance of a next encryption round.Type: GrantFiled: August 28, 2008Date of Patent: April 2, 2013Assignee: LSI CorporationInventors: Paul G. Filseth, Mikhail Grinchuk, Anatoli Bolotov, Lav D. Ivanovic
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Publication number: 20120121079Abstract: Disclosed is a cipher independent cryptographic hardware service. Cipher independent transactions are received into input slots (202). The input slots contain FIFOs to hold the transactions. The transactions are converted from cipher independent form to cipher dependent form (206) and timing as they are removed from the FIFOs. After cryptographic processing by cipher specific hardware, the results are sent to output FIFOs (212). Multiple FIFOs and cryptographic hardware may be used so that multiple cryptographic functions may be performed in parallel and simultaneously.Type: ApplicationFiled: April 10, 2009Publication date: May 17, 2012Inventors: Anatoli Bolotov, Mikhail Grinchuk, Lav Ivanovic, Christine E. Severns-Williams
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Patent number: 8160242Abstract: An apparatus including an initialization circuit and a hash computation circuit. The initialization circuit may be configured to present a number of initialization values. The hash computation circuit may be configured to generate hash values for the message in response to the padded message blocks and the initialization values. The hash computation circuit generally performs a diagonal cut technique that simultaneously uses values from a plurality of different cycle rounds in a single cycle round analog.Type: GrantFiled: October 7, 2008Date of Patent: April 17, 2012Assignee: LSI CorporationInventors: Mikhail Grinchuk, Anatoli Bolotov, Lay D. Ivanovic, Andrej A. Zolotykh, Alexei V. Galatenko
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Patent number: 8156391Abstract: A memory collar including a first circuit and a second circuit. The first circuit may be configured to generate one or more data sequences in response to one or more test commands. The one or more data sequences may be presented to a memory during a test mode. The second circuit may be configured to pre-process one or more outputs generated by the memory in response to the one or more data sequences.Type: GrantFiled: July 3, 2008Date of Patent: April 10, 2012Assignee: LSI CorporationInventors: Alexandre Andreev, Anatoli Bolotov, Mikhail Grinchuk
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Publication number: 20110320397Abstract: Disclosed is a method and apparatus for matching regular expressions. A buffer of symbols giving a number of the last occurrence positions of each symbol is maintained. When two constants match on either side of a regular expression operator, the buffer of symbols is queried to determine if a member of the complement of the regular expression operator occurred between the two constants. If so, then the operator was not satisfied. If not, then the operator was satisfied.Type: ApplicationFiled: June 24, 2010Publication date: December 29, 2011Inventors: Alexander Podkolzin, Lav Ivanovic, Anatoli Bolotov, Mikhail Grinchuk, Sergey Afonin
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Patent number: 8063659Abstract: An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.Type: GrantFiled: October 12, 2010Date of Patent: November 22, 2011Assignee: LSI CorporationInventors: Mikhail Grinchuk, Anatoli Bolotov, Sergei B. Gashkov, Lav D. Ivanovic
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Patent number: 8046643Abstract: An apparatus including a controller configured to present one or more commands and receive one or more responses, a plurality of transport circuits configured to receive one of the commands, present the responses, and generate one or more control signals, and a plurality of memory-controlling circuits, each coupled to a respective one of the plurality of transport circuits and configured to generate one or more memory access signals in response to the one or more control signals, receive one or more memory output signals from a respective memory in response to the one or more memory access signals, and generate the responses in response to the one or more memory output signals. Each respective memory may be independently sized. The controller generally provides a common testing routine for each respective memory that may be adjusted for the size of each respective memory by the memory-controlling circuits.Type: GrantFiled: July 31, 2008Date of Patent: October 25, 2011Assignee: LSI CorporationInventors: Alexandre Andreev, Anatoli Bolotov, Mikhail Grinchuk
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Patent number: 7949909Abstract: A memory collar includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first control signal, a second control signal and a third control signal in response to one or more test commands. The second circuit may be configured to generate a fourth control signal in response to said third control signal and the fourth control signal. The third circuit may be configured to generate one or more address sequences. The one or more address sequences are presented to a memory during a test mode.Type: GrantFiled: July 31, 2008Date of Patent: May 24, 2011Assignee: LSI CorporationInventors: Alexandre Andreev, Anatoli Bolotov, Mikhail Grinchuk
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Publication number: 20110029980Abstract: An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.Type: ApplicationFiled: October 12, 2010Publication date: February 3, 2011Inventors: Mikhail Grinchuk, Anatoli Bolotov, Sergei B. Gashkov, Lav D. Ivanovic
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Patent number: 7839164Abstract: An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.Type: GrantFiled: May 14, 2009Date of Patent: November 23, 2010Assignee: LSI CorporationInventors: Mikhail Grinchuk, Anatoli Bolotov, Sergei B. Gashkov, Lav D. Ivanovic