Patents by Inventor Mikhail Khapaev

Mikhail Khapaev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8701066
    Abstract: Some embodiments of the invention provide a method for verifying an integrated circuit (IC) design. The method receives a process description file that specifies a process technology for building the IC. The process description file describes a particular device type in which a first conductor overlaps a second conductor by recessing from the second conductor in one or more cut-outs. Based on the process description file, the method finds a section of the IC design that matches the particular device type and uses the description of the particular device type to compute a capacitance value and a resistance value for the section of the IC design.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: April 15, 2014
    Assignee: Cadence Design Systens, Inc.
    Inventors: Chi-Yuan Lo, Mikhail Khapaev
  • Patent number: 8689157
    Abstract: Some embodiments of the invention provide a method for verifying an integrated circuit (IC) design. The method receives a process description file that specifies a process technology for building the IC. The process description file describes a particular device type in which a first conductor overlaps a second conductor by recessing from the second conductor in one or more cut-outs. Based on the process description file, the method finds a section of the IC design that matches the particular device type and uses the description of the particular device type to compute a capacitance value and a resistance value for the section of the IC design.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: April 1, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Chi-Yuan Lo, Mikhail Khapaev