Patents by Inventor Mikhail Nagoga
Mikhail Nagoga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8659948Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.Type: GrantFiled: December 23, 2011Date of Patent: February 25, 2014Assignee: Micron Technology, Inc.Inventors: Serguei Okhonin, Mikhail Nagoga, Cedric Bassin
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Publication number: 20130322148Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.Type: ApplicationFiled: August 12, 2013Publication date: December 5, 2013Applicant: Micron Technology, Inc.Inventors: Yogesh LUTHRA, Serguei OKHONIN, Mikhail NAGOGA
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Publication number: 20130250699Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.Type: ApplicationFiled: May 21, 2013Publication date: September 26, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Serguei OKHONIN, Viktor I. KOLDIAEV, Mikhail NAGOGA, Yogesh LUTHRA
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Publication number: 20130250674Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.Type: ApplicationFiled: May 21, 2013Publication date: September 26, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Eric CARMAN, Mikhail NAGOGA, Serguei OKHONIN
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Patent number: 8537610Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.Type: GrantFiled: July 12, 2010Date of Patent: September 17, 2013Assignee: Micron Technology, Inc.Inventors: Serguei Okhonin, Viktor I Koldiaev, Mikhail Nagoga, Yogesh Luthra
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Patent number: 8508970Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.Type: GrantFiled: April 27, 2010Date of Patent: August 13, 2013Assignee: Micron Technology, Inc.Inventors: Yogesh Luthra, Serguei Okhonin, Mikhail Nagoga
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Patent number: 8446794Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.Type: GrantFiled: May 23, 2012Date of Patent: May 21, 2013Assignee: Micron Technology, Inc.Inventors: Eric Carman, Mikhail Nagoga, Serguei Okhonin
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Patent number: 8325515Abstract: A semiconductor device along with circuits including same and methods of operating same are disclosed. In one particular embodiment, the device may comprise a memory cell including a transistor. The transistor may comprise a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device may be refreshed during hold operations.Type: GrantFiled: September 2, 2011Date of Patent: December 4, 2012Assignee: Micron Technology, Inc.Inventors: Serguei Okhonin, Mikhail Nagoga
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Patent number: 8295078Abstract: An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region. First circuitry is coupled to the punch-through mode transistor of the memory cell to: (1) generate first and second sets of write control signals, and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell.Type: GrantFiled: April 22, 2011Date of Patent: October 23, 2012Assignee: Micron Technology, Inc.Inventors: Serguei Okhonin, Mikhail Nagoga
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Publication number: 20120236671Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.Type: ApplicationFiled: May 23, 2012Publication date: September 20, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Eric CARMAN, Mikhail NAGOGA, Serguei OKHONIN
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Patent number: 8194487Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.Type: GrantFiled: September 17, 2008Date of Patent: June 5, 2012Assignee: Micron Technology, Inc.Inventors: Eric Carman, Mikhail Nagoga, Serguei Okhonin
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Publication number: 20120092942Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.Type: ApplicationFiled: December 23, 2011Publication date: April 19, 2012Applicant: Micron Technology, Inc.Inventors: SERGUEI OKHONIN, Mikhail Nagoga, Cedric Bassin
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Publication number: 20120002467Abstract: A semiconductor device along with circuits including same and methods of operating same are disclosed. In one particular embodiment, the device may comprise a memory cell including a transistor. The transistor may comprise a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device may be refreshed during hold operations.Type: ApplicationFiled: September 2, 2011Publication date: January 5, 2012Applicant: Micron Technology, Inc.Inventors: Serguei Okhonin, Mikhail Nagoga
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Patent number: 8085594Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.Type: GrantFiled: May 30, 2008Date of Patent: December 27, 2011Assignee: Micron Technology, Inc.Inventors: Serguei Okhonin, Mikhail Nagoga, Cedric Bassin
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Patent number: 8014195Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device is inherently refreshed during hold operations.Type: GrantFiled: February 6, 2009Date of Patent: September 6, 2011Assignee: Micron Technology, Inc.Inventors: Serguei Okhonin, Mikhail Nagoga
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Publication number: 20110194363Abstract: An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region. First circuitry is coupled to the punch-through mode transistor of the memory cell to: (1) generate first and second sets of write control signals, and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell.Type: ApplicationFiled: April 22, 2011Publication date: August 11, 2011Applicant: Micron Technology, Inc.Inventors: Serguei Okhonin, Mikhail Nagoga
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Patent number: 7933142Abstract: An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region. First circuitry is coupled to the punch-through mode transistor of the memory cell to: (1) generate first and second sets of write control signals, and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell.Type: GrantFiled: April 30, 2007Date of Patent: April 26, 2011Assignee: Micron Technology, Inc.Inventors: Serguei Okhonin, Mikhail Nagoga
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Publication number: 20110007578Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.Type: ApplicationFiled: July 12, 2010Publication date: January 13, 2011Applicant: Innovative Silicon ISi SAInventors: Serguei Okhonin, Viktor I. Koldiaev, Mikhail Nagoga, Yogesh Luthra
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Publication number: 20100271857Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.Type: ApplicationFiled: April 27, 2010Publication date: October 28, 2010Applicant: Innovative Silicon ISi SAInventors: Yogesh Luthra, Serguei Okhonin, Mikhail Nagoga
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Patent number: 7606066Abstract: A technique of writing, programming, holding, maintaining, sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one aspect, the present inventions are directed to techniques to control and/or operate a semiconductor memory cell (and memory cell array having a plurality of such memory cells as well as an integrated circuit device including a memory cell array) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques of the present inventions may employ bipolar transistor currents to control, write and/or read a data state in such a memory cell.Type: GrantFiled: August 24, 2006Date of Patent: October 20, 2009Assignee: Innovative Silicon ISi SAInventors: Serguei Okhonin, Mikhail Nagoga