Patents by Inventor Mikhail Palityka
Mikhail Palityka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11954366Abstract: Providing constant fixed commands to memory dies within a data storage device may result in hardware and firmware overheads impacting the performance at a flash interface module (FIM) because the FIM has to handle both the constant fixed commands and the overheads associated with the constant fixed commands. To avoid the impact on performance at the FIM, multiple fixed commands may be combined into individual multi-commands that may be provided to the memory dies. The use of multi-commands reduces hardware and firmware overheads at the FIM relative to the constant fixed commands, which improves performance of the data storage device because the saturation of the FIM is decreased.Type: GrantFiled: May 26, 2022Date of Patent: April 9, 2024Assignee: Western Digital Technologies, Inc.Inventors: Dinesh Kumar Agarwal, Vijay Sivasankaran, Mikhail Palityka
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Publication number: 20240103762Abstract: Processing commands received from a host computing device by a storage device can require a large amount of processing overhead. This demand for ever greater processing power increases as the size of storage devices increase. Traditional methods have added an increasing number of processors or CPUs to handle these requirements. However, by utilizing a fast path accelerated processing pipeline, additional processors may not be necessary. An accelerated processing pipeline can be configured to bypass one or more steps that are required by non-priority processing pipelines. Each received command can be parsed to determine if it is suitable for accelerated processing. The command can be required to access data in a limited region of the memory device, or to have any data necessary to process the command already in a cache memory. Upon completion of verifications, commands can be placed in a priority queue that is processed before a non-priority queue.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Inventors: Vijay Sivasankaran, Dinesh Agarwal, Mikhail Palityka
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Patent number: 11941273Abstract: Variable Capacity Zone Namespace (ZNS) Flash Storage Data Path. In one example, a data storage device including an electronic processor that, when executing a variable capacity scheme, is configured to determine whether a special indication regarding a particular zone in a ZNS is received, delay an association of a final flash block with the particular zone, receive and stage host data for the particular zone in a staging area, receive a zone close request, compact the host data with other host data for storage in other zones into second host data, and move the second host data to the final flash block that is associated with the particular zone and the other zones. The compaction of the host data with the other host data into the second host data reduces or eliminates padding in the final flash block, and consequently, reduces overhead in the data storage device.Type: GrantFiled: May 12, 2022Date of Patent: March 26, 2024Assignee: Western Digital Technologies, Inc.Inventors: Oleg Kragel, Vijay Sivasankaran, Mikhail Palityka, Lawrence Vazhapully Jacob
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Patent number: 11922036Abstract: Host data stream assignment with space-leveling across storage block containers. In one example, a data storage device including an electronic processor that, when executing a space-leveling scheme, is configured to receive a first host data stream, store the first host data stream in a block container assignment queue (BCAQ), detect a next storage block container switching event, responsive to detecting the next storage block container switching event, randomly select a location of the BCAQ, responsive to randomly selecting the location of the BCAQ, assign a second host data stream located at the location of the BCAQ that is selected to a storage block container of a memory, and control the memory to store the second host data stream in the storage block container that is assigned.Type: GrantFiled: May 12, 2022Date of Patent: March 5, 2024Assignee: Western Digital Technologies, Inc.Inventors: Oleg Kragel, Vijay Sivasankaran, Mikhail Palityka, Lawrence Vazhapully Jacob
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Patent number: 11880604Abstract: Read Fused Groups with uniform resource allocation. In one example, a data storage device including an electronic processor that, when executing the Uniform Read Fused Group scheme, is configured to receive information indicating each zone of a plurality of Zone Namespace (ZNS) zones is assigned to one of a plurality of Read Fused Groups (RFGs), assign a portion of a plurality of resources of a memory to the plurality of ZNS zones, control all of the plurality of concurrency units to process a first resource of the plurality of resources assigned to a first Read Fused Group (RFG) of the plurality of RFGs. The first resource is assigned to a first zone of the plurality of ZNS zones, the first zone is assigned to the first RFG, and the electronic processor is one of the plurality concurrency units.Type: GrantFiled: May 12, 2022Date of Patent: January 23, 2024Assignee: Western Digital Technologies, Inc.Inventors: Oleg Kragel, Vijay Sivasankaran, Mikhail Palityka, Lawrence Vazhapully Jacob
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Publication number: 20230384974Abstract: Providing constant fixed commands to memory dies within a data storage device may result in hardware and firmware overheads impacting the performance at a flash interface module (FIM) because the FIM has to handle both the constant fixed commands and the overheads associated with the constant fixed commands. To avoid the impact on performance at the FIM, multiple fixed commands may be combined into individual multi-commands that may be provided to the memory dies. The use of multi-commands reduces hardware and firmware overheads at the FIM relative to the constant fixed commands, which improves performance of the data storage device because the saturation of the FIM is decreased.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Inventors: Dinesh Kumar Agarwal, Vijay Sivasankaran, Mikhail Palityka
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Publication number: 20230367500Abstract: Variable Capacity Zone Namespace (ZNS) Flash Storage Data Path. In one example, a data storage device including an electronic processor that, when executing a variable capacity scheme, is configured to determine whether a special indication regarding a particular zone in a ZNS is received, delay an association of a final flash block with the particular zone, receive and stage host data for the particular zone in a staging area, receive a zone close request, compact the host data with other host data for storage in other zones into second host data, and move the second host data to the final flash block that is associated with the particular zone and the other zones. The compaction of the host data with the other host data into the second host data reduces or eliminates padding in the final flash block, and consequently, reduces overhead in the data storage device.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Inventors: Oleg Kragel, Vijay Sivasankaran, Mikhail Palityka, Lawrence Vazhapully Jacob
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Publication number: 20230367499Abstract: Host data stream assignment with space-leveling across storage block containers. In one example, a data storage device including an electronic processor that, when executing a space-leveling scheme, is configured to receive a first host data stream, store the first host data stream in a block container assignment queue (BCAQ), detect a next storage block container switching event, responsive to detecting the next storage block container switching event, randomly select a location of the BCAQ, responsive to randomly selecting the location of the BCAQ, assign a second host data stream located at the location of the BCAQ that is selected to a storage block container of a memory, and control the memory to store the second host data stream in the storage block container that is assigned.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Inventors: Oleg Kragel, Vijay Sivasankaran, Mikhail Palityka, Lawrence Vazhapully Jacob
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Publication number: 20230367512Abstract: Read Fused Groups with uniform resource allocation. In one example, a data storage device including an electronic processor that, when executing the Uniform Read Fused Group scheme, is configured to receive information indicating each zone of a plurality of Zone Namespace (ZNS) zones is assigned to one of a plurality of Read Fused Groups (RFGs), assign a portion of a plurality of resources of a memory to the plurality of ZNS zones, control all of the plurality of concurrency units to process a first resource of the plurality of resources assigned to a first Read Fused Group (RFG) of the plurality of RFGs. The first resource is assigned to a first zone of the plurality of ZNS zones, the first zone is assigned to the first RFG, and the electronic processor is one of the plurality concurrency units.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Inventors: Oleg Kragel, Vijay Sivasankaran, Mikhail Palityka, Lawrence Vazhapully Jacob
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Patent number: 11803333Abstract: Read Fused Groups with uniform resource allocation. In one example, a data storage device including an electronic processor that, when executing the Uniform Read Fused Group scheme, is configured to receive information indicating each zone of a plurality of Zone Namespace (ZNS) zones is assigned to one of a plurality of Read Fused Groups (RFGs), assign a portion of a plurality of resources of a memory to the plurality of ZNS zones, control all of the plurality of concurrency units to process a first resource of the plurality of resources assigned to a first Read Fused Group (RFG) of the plurality of RFGs. The first resource is assigned to a first zone of the plurality of ZNS zones, the first zone is assigned to the first RFG, and the electronic processor is one of the plurality concurrency units.Type: GrantFiled: May 12, 2022Date of Patent: October 31, 2023Assignee: Western Digital Technologies, Inc.Inventors: Oleg Kragel, Vijay Sivasankaran, Mikhail Palityka, Lawrence Vazhapully Jacob
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Publication number: 20230017171Abstract: Increases in efficiency of storage device operation may be realized if the limited number of available high-priority communication channels are better optimized and assigned among hosts that may best utilize them. This assignment can occur in response to an evaluation of the overall zone usage or by received metadata and/or indicia from the host. The storage device may periodically, or in response to a command, reevaluate the assigned priority status of each communication channel and associated host/zone pair. For example, the storage device may demote or remove a communication channel from high-priority to low-priority. This process can be continued during a preconfigured time window which can be adjusted before, during, or after priority evaluation. The continuous operation of this process can allow for adjustments being made to priority levels within the storage device that may further increase total operational efficiency.Type: ApplicationFiled: September 19, 2022Publication date: January 19, 2023Inventors: Oleg Kragel, Xiangyu Tang, Vijay Sivasankaran, Mikhail Palityka
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Patent number: 11449443Abstract: Increases in efficiency of storage device operation may be realized if the limited number of available high-priority communication channels are better optimized and assigned among hosts that may best utilize them. This assignment can occur in response to an evaluation of the overall zone usage or by received metadata and/or indicia from the host. The storage device may periodically, or in response to a command, reevaluate the assigned priority status of each communication channel and associated host/zone pair. For example, the storage device may demote or remove a communication channel from high-priority to low-priority. This process can be continued during a preconfigured time window which can be adjusted before, during, or after priority evaluation. The continuous operation of this process can allow for adjustments being made to priority levels within the storage device that may further increase total operational efficiency.Type: GrantFiled: February 26, 2021Date of Patent: September 20, 2022Assignee: Western Digital Technologies, Inc.Inventors: Oleg Kragel, Xiangyu Tang, Vijay Sivasankaran, Mikhail Palityka
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Publication number: 20220121587Abstract: Increases in efficiency of storage device operation may be realized if the limited number of available high-priority communication channels are better optimized and assigned among hosts that may best utilize them. This assignment can occur in response to an evaluation of the overall zone usage or by received metadata and/or indicia from the host. The storage device may periodically, or in response to a command, reevaluate the assigned priority status of each communication channel and associated host/zone pair. For example, the storage device may demote or remove a communication channel from high-priority to low-priority. This process can be continued during a preconfigured time window which can be adjusted before, during, or after priority evaluation. The continuous operation of this process can allow for adjustments being made to priority levels within the storage device that may further increase total operational efficiency.Type: ApplicationFiled: February 26, 2021Publication date: April 21, 2022Inventors: Oleg Kragel, Xiangyu Tang, Vijay Sivasankaran, Mikhail Palityka
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Patent number: 10489077Abstract: Systems and methods are disclosed for executing access commands for a data storage device. A data storage device receives first data to be written to a plurality of dies/non-volatile memory arrays. The data storage device transfers a first metapage of the first data to the plurality of dies/non-volatile memory arrays. The data storage device also programs the first metapage to a first metablock of the plurality of dies and programs the first metapage to a second metablock of the plurality of dies/non-volatile memory arrays. The data storage device further transfers a second metapage to the plurality of dies/non-volatile memory arrays. Programming the first metapage to the first metablock may be simultaneous with transferring the second metapage to the plurality of dies/non-volatile memory arrays.Type: GrantFiled: May 28, 2017Date of Patent: November 26, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Sourabh Sankule, Avinash Sharma, Mikhail Palityka
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Publication number: 20180341406Abstract: Systems and methods are disclosed for executing access commands for a data storage device. A data storage device receives first data to be written to a plurality of dies/non-volatile memory arrays. The data storage devices transfers a first metapage of the first data to the plurality of dies/non-volatile memory arrays. The data storage device also programs the first metapage to a first metablock of the plurality of dies and programs the first metapage to a second metablock of the plurality of dies/non-volatile memory arrays. The data storage device further transfers a second metapage to the plurality of dies/non-volatile memory arrays. Programming the first metapage to the first metablock may be simultaneous with transferring the second metapage to the plurality of dies/non-volatile memory arrays.Type: ApplicationFiled: May 28, 2017Publication date: November 29, 2018Inventors: Sourabh SANKULE, Avinash SHARMA, Mikhail PALITYKA
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Patent number: 9858009Abstract: Data that is initially stored in Single Level Cell (SLC) blocks is subsequently copied (folded) to a Multi Level Cell (MLC) block where the data is stored in MLC format, the data copied in a minimum unit of a fold-set, the MLC block including a plurality of separately-selectable sets of NAND strings, data of an individual fold-set copied exclusively to two or more word lines of an individual separately-selectable set of NAND strings in the MLC block.Type: GrantFiled: October 26, 2015Date of Patent: January 2, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Abhijeet Bhalerao, Mrinal Kochar, Dennis S. Ea, Mikhail Palityka, Aaron Lee, Yew Yin Ng, Ivan Baran
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Patent number: 9792175Abstract: When the number of bad columns in a memory or plane is less than a threshold number then a first Error Correction Code (ECC) scheme encodes user data in first pages of a first size. If the number of bad columns is greater than the threshold number then a second ECC scheme encodes the user data in second pages of a second size that is smaller than the first size.Type: GrantFiled: October 21, 2015Date of Patent: October 17, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Sahil Sharma, Abhijeet Manohar, Mrinal Kochar, Yong Huang, Derek McAuley, Mikhail Palityka, Ivan Baran, Aaron Lee
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Patent number: 9760303Abstract: Partially-bad blocks are identified in a 3-D block-erasable nonvolatile memory, each partially-bad block having one or more inoperable separately-selectable sets of NAND strings and one or more operable separately-selectable sets of NAND strings. Operable sets of NAND strings within two or more partially-bad blocks are identified and are mapped to form one or more virtual blocks that are individually assigned virtual block addresses. The virtual block address are maintained in a list and used to access the virtual blocks.Type: GrantFiled: September 29, 2015Date of Patent: September 12, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Dennis S. Ea, Ivan Baran, Aaron Lee, Mrinal Kochar, Mikhail Palityka, Yew Yin Ng, Abhijeet Bhalerao
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Patent number: 9728262Abstract: Non-volatile memory systems with multi-write direction memory units are disclosed. In one implementation an apparatus comprises a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to select an empty memory block of the non-volatile memory for the storage of data; examine an identifier associated with the memory block to determine a write direction for the storage of data; and write data to the memory block beginning with an initial word line of the memory block or a last word line of the memory block dependent on the write direction. The controller is further configured to erase the memory unit and, in response to erasing the memory unit, modify the identifier to change the write direction for a subsequent write of data to the memory block.Type: GrantFiled: October 30, 2015Date of Patent: August 8, 2017Assignee: SanDisk Technologies LLCInventors: Ivan Baran, Aaron Lee, Mrinal Kochar, Mikhail Palityka, Dennis Ea, Yew Yin Ng, Abhijeet Bhalerao
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Publication number: 20170125104Abstract: Non-volatile memory systems with multi-write direction memory units are disclosed. In one implementation an apparatus comprises a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to select an empty memory block of the non-volatile memory for the storage of data; examine an identifier associated with the memory block to determine a write direction for the storage of data; and write data to the memory block beginning with an initial word line of the memory block or a last word line of the memory block dependent on the write direction. The controller is further configured to erase the memory unit and, in response to erasing the memory unit, modify the identifier to change the write direction for a subsequent write of data to the memory block.Type: ApplicationFiled: October 30, 2015Publication date: May 4, 2017Applicant: SanDisk Technologies Inc.Inventors: Ivan Baran, Aaron Lee, Mrinal Kochar, Mikhail Palityka, Dennis Ea, Yew Yin Ng, Abhijeet Bhalerao