Abstract: A voltage regulator having a multiple of main stages and at least one accelerated voltage regulator (AVR) bridge is provided. The main stages may respond to low frequency current transients and provide DC output voltage regulation. The AVR bridges are switched much faster than the main stages and respond to high frequency current transients without regulating the DC output voltage. The AVR bridge frequency response range can overlap with the main stage frequency response range, and the lowest frequency to which the AVR bridges respond may be set lower than the highest frequency to which the main stages respond.

Abstract: A voltage supervisor (VS) or voltage sensing circuitry or architecture that can detect fast voltage transients. To detect fast voltage transients, a dedicated differential pair is routed between a point of load, such as a die or other chip, processor, etc., and the circuitry of the voltage supervisor. By connecting the differential pair at the point of load, fast voltage transients may be detected at the load level (e.g., at the point of load) and thereafter used to enable, disable, and/or restart an electronic device, such as a die, chip, processor, or other electronic component or system.

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

Abstract: An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connecter of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.

Abstract: Systems and methods for resonance aware performance management of processing devices. In one aspect, a method includes iteratively testing a performance operation for the processing device, wherein each iteration is performed at an iteration voltage level for a power delivery network. The performance operation is applied at different application periods and at the iteration voltage level for the iteration. If no failure condition is met, the iteration voltage is reduced and another iteration is done. Upon a failure occurring at a particular application period, an operational voltage level for the power delivery network that is based on the iteration voltage level for the iteration in which a failure condition was induced is selected, and application of the performance operation at the particular application period is precluded.

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

Abstract: Systems and methods for resonance aware performance management of processing devices. In one aspect, a method includes iteratively testing a performance operation for the processing device, wherein each iteration is performed at an iteration voltage level for a power delivery network. The performance operation is applied at different application periods and at the iteration voltage level for the iteration. If no failure condition is met, the iteration voltage is reduced and another iteration is done. Upon a failure occurring at a particular application period, an operational voltage level for the power delivery network that is based on the iteration voltage level for the iteration in which a failure condition was induced is selected, and application of the performance operation at the particular application period is precluded.

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

Abstract: Systems and methods for resonance aware performance management of processing devices. In one aspect, a method includes iteratively testing a performance operation for the processing device, wherein each iteration is performed at an iteration voltage level for a power delivery network. The performance operation is applied at different application periods and at the iteration voltage level for the iteration. If not failure condition is met, the iteration voltage is reduced and another iteration is done. Upon a failure occurring at a particular application period, an operational voltage level for the power delivery network that is based on the iteration voltage level for the iteration in which a failure condition was induced is selected, and application of the performance operation at the particular application period is precluded.

Abstract: This disclosure relates to power balancer circuits that enable multiple load zones of an IC to be powered in series while maintaining balanced voltage at each load zone. In one aspect, a circuit includes load zones that are powered in series. The circuit includes a power balancer for balancing a voltage across each load zone. The power balancer includes an equivalent DC transformer array that includes, for each load zone, an equivalent DC transformer connected in parallel with the load zone. The power balancer includes, for each load zone, a bus capacitor connected in parallel with the load zone. Each equivalent DC transformer is electrically connected to each other equivalent DC transformer providing an electrical path for each bus capacitor to discharge current to each other bus capacitor when a voltage across a bus capacitor is greater than a voltage across another bus capacitor.

Abstract: The place and route stage for a hard macro is modified to assign a more robust power-grid tier to a critical path for a hard macro and to assign a less robust power-grid tier to a remainder of the hard macro.

Abstract: An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connecter of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.

Abstract: Systems and methods for resonance aware performance management of processing devices. In one aspect, a method includes iteratively testing a performance operation for the processing device, wherein each iteration is performed at an iteration voltage level for a power delivery network. The performance operation is applied at different application periods and at the iteration voltage level for the iteration. If not failure condition is met, the iteration voltage is reduced and another iteration is done. Upon a failure occurring at a particular application period, an operational voltage level for the power delivery network that is based on the iteration voltage level for the iteration in which a failure condition was induced is selected, and application of the performance operation at the particular application period is precluded.

Abstract: An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connector of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.

Abstract: In certain aspects, an integrated circuit comprises a first circuit macro having a first power delivery network, a second circuit macro having a second power delivery network. The integrated circuit further comprises a coupling circuit couples to the first power delivery network and to the second power delivery network.

Abstract: The place and route stage for a hard macro is modified to assign a more robust power-grid tier to a critical path for a hard macro and to assign a less robust power-grid tier to a remainder of the hard macro.

Abstract: The place and route stage for a hard macro including a plurality of tiles is modified so that some of the tiles are assigned a more robust power-grid tier and so that others ones of the tiles are assigned a less robust power-grid tier.

Abstract: In certain aspects, an integrated circuit comprises a first circuit macro having a first power delivery network, a second circuit macro having a second power delivery network. The integrated circuit further comprises a coupling circuit couples to the first power delivery network and to the second power delivery network.