Abstract: Methods and apparatus for implementing Brownian Bridge algorithm on Single Instruction Multiple Data (SIMD) computing platforms are described. In one embodiment, a memory stores a plurality of data corresponding to an SIMD (Single Instruction, Multiple Data) instruction. A processor may include a plurality of SIMD lanes. Each of the plurality of the SIMD lanes may process one of the plurality of data stored in the memory in accordance with the SIMD instruction. Other embodiments are also described.

Abstract: In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.

Abstract: An extended TMU system of a graphics system is disclosed. The extended TMU system includes a novel parameter, which allows the texture mapping unit to obtain multiple samples, calculate a dot product for the multiple samples, and return a sample of a maximum dot product value, all in a single call. The extended TMU system speeds up the performance of a primitive operation essential to collision detection. Compared to other approaches, the extended TMU system reduce the amount of data transferred during the primitive computation between the core and the TMU by around 75%, and also improves the throughput between 10%-40% for three fundamental collision detection algorithms.

Abstract: A technique to perform concurrent updates to a shared data structure. At least one embodiment of the invention concurrently stores copies of a data structure within a plurality of local caches, updates the local caches with a partial result of a computation distributed among a plurality of processing elements, and returns the partial results to combining logic in parallel, which combines the partial results into a final result.

Abstract: Methods and apparatus to provide virtualized vector processing are described. In one embodiment, one or more operations corresponding to a virtual vector request are distributed to one or more processor cores for execution.

Abstract: In one embodiment, the present invention includes a method for performing a first level task of an application in a first processor of a system and dynamically allocating a second level task of the application to one of the first processor and a second processor based on architectural feedback information. In this manner, improved scheduling and application performance can be achieved by better utilizing system resources. Other embodiments are described and claimed.

Abstract: A technique to perform concurrent updates to a shared data structure. At least one embodiment of the invention concurrently stores copies of a data structure within a plurality of local caches, updates the local caches with a partial result of a computation distributed among a plurality of processing elements, and returns the partial results to combining logic in parallel, which combines the partial results into a final result.