Abstract: A packet switch has pluralities of incoming and outgoing trunks, a data memory accessible from them in common, and FIFO memories each provided in each of input and output circuits. Data from the incoming trunks is written into and read out from the buffer memory for transfer to the outgoing trunks, on a time-shared basis, to perform packet switching between trunks of different data transfer rates. Furthermore, the packet switch has an arbiter for detecting process requests from the input circuits and an arbiter for detecting process requests from the output circuits, so that priority control is effected for servicing the requests. As a result, dynamic allocation of access to the buffer memory to the input and output circuits is permitted.