Abstract: An information processing device includes processing circuitry configured to; acquire target area information indicating a situation of a target area, use schedule information indicating a use schedule of a mobile body by a user in the target area, and space reservation information indicating a use reservation of a space in the target area; determine a use mode of the space for the mobile body depending on convenience of the user in the target area on a basis of the target area information and the use schedule information; and update the space reservation information on a basis of the determined use mode.

Abstract: A circuit includes: a first line to which input and output signal terminals are connected; a first transistor having a first terminal connected to the first line, a second terminal connected to a ground potential, and a control terminal supplied with a first oscillation signal, the first transistor outputting the first signal and its harmonic component; a second transistor having a first terminal connected to the first line, a second terminal connected to the ground potential, and a control terminal supplied with a second oscillation signal, the second transistor outputting the second signal and its harmonic component; a first harmonic generator connected to the control terminal of the first transistor and generates a harmonic component including the harmonic component by the first transistor; and a second harmonic generator connected to the control terminal of the second transistor and generates a harmonic component including the harmonic component by the second transistor.

Abstract: An electronic circuit includes a first transistor having a first terminal grounded, a second transistor having a control terminal coupled with a second terminal of the first transistor, a first terminal grounded via a first capacitor, and a second terminal to which a DC power supply is connected, a first distributed constant line having one end connected to a first node between the second terminal of the first transistor and the control terminal of the second transistor and another end grounded via a second capacitor, a second distributed constant line having one end connected to the second terminal of the first transistor and another end connected to the first node, a third distributed constant line having one end connected to the control terminal of the second transistor and another end connected to the first node, a resistor connected between a second node between the first line and the second capacitor and a third node between the first terminal of the second transistor and the first capacitor, and a path

Abstract: A circuit includes: a first line to which input and output signal terminals are connected; a first transistor having a first terminal connected to the first line, a second terminal connected to a ground potential, and a control terminal supplied with a first oscillation signal, the first transistor outputting the first signal and its harmonic component; a second transistor having a first terminal connected to the first line, a second terminal connected to the ground potential, and a control terminal supplied with a second oscillation signal, the second transistor outputting the second signal and its harmonic component; a first harmonic generator connected to the control terminal of the first transistor and generates a harmonic component including the harmonic component by the first transistor; and a second harmonic generator connected to the control terminal of the second transistor and generates a harmonic component including the harmonic component by the second transistor.

Abstract: An electronic circuit includes a first transistor having a first terminal grounded, a second transistor having a control terminal coupled with a second terminal of the first transistor, a first terminal grounded via a first capacitor, and a second terminal to which a DC power supply is connected, a first distributed constant line having one end connected to a first node between the second terminal of the first transistor and the control terminal of the second transistor and another end grounded via a second capacitor, a second distributed constant line having one end connected to the second terminal of the first transistor and another end connected to the first node, a third distributed constant line having one end connected to the control terminal of the second transistor and another end connected to the first node, a resistor connected between a second node between the first line and the second capacitor and a third node between the first terminal of the second transistor and the first capacitor, and a path

Abstract: An input buffer circuit 11X is a source follower circuit and comprises a load 114 and enhancement FETs 111 and 112A connected in series between power supply lines VDD and VSS. A DC bias VB1 is applied to the gate of the FET 112A to act it as a current source, and an AC current component of the drain potential VD of the FET 111 is provided through a capacitor 113 to the gate of the FET 112A. If an inductor as an matching circuit is connected in series to the capacitor 113, a band pass filter is constructed, and the gain of the circuit 11X becomes especially high at the resonance frequency thereof. At high frequencies, the interconnection coupled to the capacitor 113 has a parasitic inductance, and the output waveform of the circuit 11X has a high frequency noise. In this case, a damping transistor is connected between the capacitor 113 and the gate of the FET 112A to obtain a flat gain by adjusting the gate potential thereof.

Abstract: An input buffer circuit 11X is a source follower circuit and comprises a load 114 and enhancement FETs 111 and 112A connected in series between power supply lines VDD and VSS. A DC bias VB1 is applied to the gate of the FET 112A to act it as a current source, and an AC current component of the drain potential VD of the FET 111 is provided through a capacitor 113 to the gate of the FET 112A. If an inductor as an matching circuit is connected in series to the capacitor 113, a band pass filter is constructed, and the gain of the circuit 11X becomes especially high at the resonance frequency thereof. At high frequencies, the interconnection coupled to the capacitor 113 has a parasitic inductance, and the output waveform of the circuit 11X has a high frequency noise. In this case, a damping transistor is connected between the capacitor 113 and the gate of the FET 112A to obtain a flat gain by adjusting the gate potential thereof.

Abstract: A semiconductor integrated circuit has a first load device and a first switching device connected in series between a first power supply line and a second power supply line, and an input signal is supplied to the control terminal of the first switching device. The semiconductor integrated circuit has a first switch unit and a first load unit. The first switch unit is connected between the first load device and the first power supply line, and is supplied with a first control signal at its control terminal. The first load unit is connected to the control terminal of the first switch unit, and its impedance is set at or varied to an arbitrary value. The band, gain, and output voltage of the circuit are controlled by the first control signal and the impedance of the first load unit. With this configuration, the gain and band (operating frequency band) of an amplifier constructed from an FET can be increased.

Abstract: A frequency dividing circuit includes a first inverter circuit supplied with a first frequency-divided signal, a second inverter circuit supplied with a second frequency-divided signal which has a complementary relationship to the first frequency-divided signal, and a first pair of push-pull circuits. There are also provided a first switch circuit performing a first switching operation in response to a first input signal and selectively supplying output signals of the first and second inverter circuits to the first pair of push-pull circuits so that one of the first pair of push-pull circuits performs a pull-up operation when the other one thereof performs a pull-down operation.

Abstract: A transfer gate circuit has a FET 1 and FET 2 connected in series each other, both gates of which are connected commonly. The threshold voltage of the FET 1 is lower than that of the FET 2. A dynamic divider circuit has this transfer gate circuit connected between an output of one source follower circuit and an input of another source follower circuit.