Patents by Inventor Miki Matsumoto

Miki Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11972123
    Abstract: Methods, systems, and devices for row address latching for multiple activate command protocol are described. A memory device may receive a first activate command that indicates a first set of bits of a row address and may store the first set of bits to obtain a first delayed signal of the first set of bits. The memory device may receive a second activate command that indicates a second set of bits of the row address and may store the second set of bits to obtain a first delayed signal of the second set of bits. The memory device may store the first delayed signal of the first set of bits to obtain a second delayed signal of the first set of bits and may activate a page of memory addressed according to the second delayed signal and the first delayed signal of the second set of bits.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: April 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kwang-Ho Cho, Miki Matsumoto
  • Publication number: 20240069760
    Abstract: Methods, systems, and devices for row address latching for multiple activate command protocol are described. A memory device may receive a first activate command that indicates a first set of bits of a row address and may store the first set of bits to obtain a first delayed signal of the first set of bits. The memory device may receive a second activate command that indicates a second set of bits of the row address and may store the second set of bits to obtain a first delayed signal of the second set of bits. The memory device may store the first delayed signal of the first set of bits to obtain a second delayed signal of the first set of bits and may activate a page of memory addressed according to the second delayed signal and the first delayed signal of the second set of bits.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Kwang-Ho Cho, Miki Matsumoto
  • Publication number: 20240069759
    Abstract: Methods, systems, and devices for triple activate command row address latching are described. For instance, a memory device may receive a first activate command that indicates a first set of bits of a row address, a second activate command that indicates a second set of bits of the row address, and a third activate command that indicates a third set of bits of the row address. The memory device may activate a page of memory based on receiving the first activate command, the second activate command, and the third activate command, where the page of memory is addressed according to the first set of bits, the second set of bits, and the third set of bits.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Kwang-Ho Cho, Miki Matsumoto, Kevin J. Ryan
  • Patent number: 5801554
    Abstract: A semiconductor integrated circuit device is provided having a low-amplitude input/output interface for inputting or outputting an input/output signal synchronously with a clock signal and transferring the input/output signal with an amplitude corresponding to a power supply voltage to or from an external command unit. A first differential circuit to be practically continuously operated is used as an input circuit for receiving a clock signal supplied from an external clock unit. In addition, a second differential circuit is provided which is intermittently operated in accordance with the clock signal to sample an input signal in accordance with an internal clock signal generated by the first differential circuit while the second differential circuit is operated and holds the sampled signal while the second differential circuit is not operated. This second differential circuit is used as an input circuit for receiving a low-amplitude input signal inputted synchronously with the clock signal.
    Type: Grant
    Filed: July 3, 1996
    Date of Patent: September 1, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Atsuko Momma, Miki Matsumoto, Kanji Oishi
  • Patent number: 5598372
    Abstract: A semiconductor memory incorporating an operation circuit for carrying out logical operations on data and arithmetic operations on address signals. The memory is arranged functionally so that the data representing the result of each of such operations is written to a memory array while also being output through an external terminal in the same memory cycle.
    Type: Grant
    Filed: July 25, 1995
    Date of Patent: January 28, 1997
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Miki Matsumoto, Kanji Oishi, Masahiro Katayama, Kazufumi Watanabe
  • Patent number: 5497353
    Abstract: A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed.
    Type: Grant
    Filed: March 30, 1995
    Date of Patent: March 5, 1996
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Katsuyuki Sato, Miki Matsumoto, Sadayuki Ohkuma, Masahiro Ogata, Masahiro Yoshida
  • Patent number: 5436870
    Abstract: A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed.
    Type: Grant
    Filed: August 3, 1994
    Date of Patent: July 25, 1995
    Assignees: Hitachi, Ltd., VLSI Engineering Corp.
    Inventors: Katsuyuki Sato, Miki Matsumoto, Sadayuki Ohkuma, Masahiro Ogata, Masahiro Yoshida
  • Patent number: 5323354
    Abstract: A multi-port memory is provided which is capable of being backed up by a battery to provide a resume function for a digital processor. In a preferred embodiment, a resume function can be provided for a VRAM without restricting the bit rate of image data or the function of the frame memory. Preferably, the memory includes a memory array MARY of memory cells of stereoscopic structure. A high voltage VCH for word line selection can be generated by a voltage-doubling word boost circuit which has its boosting ratio switched stepwise in accordance with the potential of an internal supply voltage. Moreover, a substrate potential generator is provided which has a first substrate potential generator having a relatively low current supplying capacity, which is steadily brought into an operative state, and a second substrate potential generator having a relatively high current supplying capacity which is selectively brought into an operative state.
    Type: Grant
    Filed: February 18, 1992
    Date of Patent: June 21, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Miki Matsumoto, Katsuyuki Sato
  • Patent number: 5323033
    Abstract: The present invention disposes a redundancy logic device and a redundancy line which are used selectively in place of a logic device or a line, which becomes unusable, in a logic portion of a semiconductor integrated circuit device such as a gate array integrated circuit.
    Type: Grant
    Filed: August 4, 1992
    Date of Patent: June 21, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Miki Matsumoto, Hiroshi Kawamoto
  • Patent number: 5313423
    Abstract: A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed.
    Type: Grant
    Filed: September 3, 1991
    Date of Patent: May 17, 1994
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Katsuyuki Sato, Miki Matsumoto, Sadayuki Ohkuma, Masahiro Ogata, Masahiro Yoshida
  • Patent number: 5289428
    Abstract: A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed.
    Type: Grant
    Filed: November 6, 1992
    Date of Patent: February 22, 1994
    Assignee: Hitachi Ltd., and Hitachi VLSI Engineering Corp.
    Inventors: Katsuyuki Sato, Miki Matsumoto, Sadayuki Ohkuma, Masahiro Ogata, Masahiro Yoshida
  • Patent number: 5278839
    Abstract: A semiconductor integrated circuit which has the function of self-checking defective bits, and which informs the exterior of its status when it has reached the status incapable of self-repair due to the limitation of the storage capacity of hardware for repairing the defective bits.
    Type: Grant
    Filed: April 16, 1991
    Date of Patent: January 11, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Miki Matsumoto, Hiroshi Kawamoto
  • Patent number: 5115413
    Abstract: A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed.
    Type: Grant
    Filed: March 20, 1990
    Date of Patent: May 19, 1992
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corporation
    Inventors: Katsuyuki Sato, Miki Matsumoto, Sadayuki Ohkuma, Masahiro Ogata, Masahiro Yoshida