Abstract: A state control circuit gives an inactive state control signal to a CPU and an active state control signal to a data transmission circuit. In response to this, the CPU goes into the halt state and the data transmission circuit goes into the receive state. When receive processing is completed, the state control circuit gives an active state control signal to the CPU. In response to this, the CPU restores from the halt state to the operative state. The CPU gives an instruction signal to the state control circuit. The state control circuit gives an inactive state control signal to the data transmission circuit. In response to this, the data transmission circuit goes into the halt state.

Abstract: A memory card includes a first nonvolatile memory, a second nonvolatile memory, and a separating portion. The first nonvolatile memory has a predetermined erase unit. The second nonvolatile memory has an erase unit that is larger than the erase unit of the first nonvolatile memory. The separating portion separates at least the portion of the program data that are downloaded onto the memory card that has the possibility of being rewritten, and stores the separated portion onto the first nonvolatile memory and stores the remaining portion onto the second nonvolatile memory.

Abstract: A memory card includes a first nonvolatile memory, a second nonvolatile memory, and a separating portion. The first nonvolatile memory has a predetermined erase unit. The second nonvolatile memory has an erase unit that is larger than the erase unit of the first nonvolatile memory. The separating portion separates at least the portion of the program data that are downloaded onto the memory card that has the possibility of being rewritten, and stores the separated portion onto the first nonvolatile memory and stores the remaining portion onto the second nonvolatile memory.

Abstract: A memory card includes a nonvolatile memory chip and a controller chip. The controller chip includes a first encrypting portion and a second encrypting portion. The first encrypting portion decrypts data input to the memory card that have been encrypted using a first key that is different for each session, using the first key. The second encrypting portion encrypts the data that are decrypted by the first encrypting portion using a second key. The nonvolatile memory chip stores the data encrypted by the second encrypting portion.

Abstract: A state control circuit (107) gives an inactive state control signal (S2) to a CPU (105) and an active state control signal (S3) to a data transmission circuit (102). In response to this, the CPU (105) goes into the halt state and the data transmission circuit (102) goes into the receive state. When receive processing is completed, the state control circuit (107) gives an active state control signal (S2) to the CPU (105). In response to this, the CPU (105) restores from the halt state to the operative state. The CPU (105) gives an instruction signal (CMD2) to the state control circuit (107). The state control circuit (107) gives an inactive state control signal (S3) to the data transmission circuit (102). In response to this, the data transmission circuit (102) goes into the halt state.