Patents by Inventor Miki Mori

Miki Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5959363
    Abstract: A semiconductor device comprising a wiring circuit board and a semiconductor chip mounted through a bump electrode on the circuit board, a space between the circuit board and the semiconductor chip as well as a periphery of the semiconductor chip being encapsulated with a resin containing a filler. The resin is constituted by a first resin disposed in a region surrounded by bump electrodes positioned on the outermost periphery of the semiconductor chip, and by a second resin disposed in a region not surrounded by bump electrodes positioned on the outermost periphery of the semiconductor chip, the first and second resins being distinct from each other in at least one feature selected from a content, a maximum particle diameter and an average particle diameter of the filler.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: September 28, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Yamada, Takasi Togasaki, Masayuki Saito, Soichi Honma, Miki Mori, Kazuki Tateyama
  • Patent number: 5864178
    Abstract: A semiconductor device comprising a wiring circuit board and a semiconductor chip mounted through a bump electrode on the circuit board, a space between the circuit board and the semiconductor chip as well as a periphery of the semiconductor chip being encapsulated with a resin containing a filler. The resin is constituted by a first resin disposed in a region surrounded by bump electrodes positioned on the outermost periphery of the semiconductor chip, and by a second resin disposed in a region not surrounded by bump electrodes positioned on the outermost periphery of the semiconductor chip, the first and second resins being distinct from each other in at least one feature selected from a content, a maximum particle diameter and an average particle diameter of the filler.
    Type: Grant
    Filed: January 3, 1996
    Date of Patent: January 26, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Yamada, Takasi Togasaki, Masayuki Saito, Soichi Honma, Miki Mori, Kazuki Tateyama
  • Patent number: 5821627
    Abstract: An electronic circuit device includes a substrate, a wiring layer formed on the surface of the substrate and essentially consisting of at least one metal selected from the group consisting of gold, copper, tin, and aluminum, a bump formed on the wiring layer and essentially consisting of at least one metal selected from the group consisting of gold, copper, and aluminum, and a micro electronic element formed on the bump, wherein solid-phase diffusion bonding is performed at least either between the wiring layer and the bump or between the bump and an electrode of the micro electronic element.
    Type: Grant
    Filed: November 5, 1997
    Date of Patent: October 13, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Miki Mori, Yukio Kizaki, Takaaki Yasumoto, Koji Yamakawa, Masayuki Saito, Tatsuro Uchida, Takasi Togasaki, Takashi Yebisuya, Taijun Murakami
  • Patent number: 5801797
    Abstract: The image display apparatus is capable of displaying an image on a large screen in which non-display regions are completely eliminated or minimized. The image display apparatus comprises an opposite board in which common electrodes made of transparent conductive resin are respectively formed on both surfaces of a transparent substrate. A plurality of array boards in each of which semiconductor element and a signal line are formed on a transparent substrate are arranged on both surfaces of the opposite board, such that display regions of end portions of the array boards face each other a sandwich of the opposite board inserted therebetween. Frame-like sealing members made of transparent resin are respectively inserted in clearances between the opposite board and the array boards. Liquid crystal is enclosed in each of spaces surrounded by the frame-like sealing members between the opposite board and the array boards.
    Type: Grant
    Filed: March 13, 1997
    Date of Patent: September 1, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Iida, Tatsuro Uchida, Akira Kinno, Masayuki Saito, Yukio Kizaki, Takeshi Miyagi, Miki Mori, Yumi Fukuda
  • Patent number: 5712493
    Abstract: A display device comprising a substrate, a rectangular display section provided on the substrate and having four sides, a plurality of driving semiconductor elements formed on peripheral portions of the substrate in the vicinity of the display section, each of the driving semiconductor elements having two opposite long sides and two opposite short sides, one of the two long sides being opposed to one side of the display section, a plurality of output lines extending from the one long side of each of the driving semiconductor elements to the display section, to output signals from the driving semiconductor elements to the display section, a plurality of input lines extending from both the short sides of each of the driving semiconductor elements, to input signals to the driving semiconductor elements to drive them, a plurality of output terminals formed on each of the driving semiconductor elements along both the long sides thereof, and electrically connected to the output lines, the number of the output termi
    Type: Grant
    Filed: March 18, 1996
    Date of Patent: January 27, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Miki Mori, Chiaki Takubo, Takeshi Sasaki
  • Patent number: 5684677
    Abstract: An electronic circuit device comprising a printed wiring board having a major surface and pads provided on the major surface of the printed wiring board, a plurality of electrodes provided partly on at least one major surface of the leadless component and partly on sides of the leadless component, a plurality of bumps provided on the pads, providing a gap between the major surface of the printed wiring board and the major surface of the leadless component, and electrically connecting those parts of the electrodes which are provided on the major surface of the leadless component to the pads, and a plurality of electrically conductive members integral with the bumps, extending from the bumps to those parts of the electrodes which are provided on the sides of the leadless component.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: November 4, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuro Uchida, Takashi Yebisuya, Miki Mori, Masayuki Saito, Takasi Togasaki, Yukio Kizaki
  • Patent number: 5594768
    Abstract: A laminograph including, a radiation source for generating radiation towards a subject, a radiation surface sensor device with a two-dimensional resolution, fitted opposite to the radiation source for detecting the radiation from the radiation source which has passed through the subject, a scanning device for moving the subject to take a plurality of different positions between the radiation source and the radiation surface sensor device and for scanning the subject in each of the different positions by the radiation from the radiation source.
    Type: Grant
    Filed: May 11, 1995
    Date of Patent: January 14, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masashi Fujii, Kiichiro Uyama, Takeo Tsuchiya, Miki Mori, Hideo Kosuge, Hirokatsu Suzuki
  • Patent number: 5499128
    Abstract: The columnar spacer included in a liquid crystal display device is formed of a photosensitive resin selected from the group consisting of acrylic polymers and acrylic copolymers, said photosensitive resin having at least one atomic group selected from the group consisting of an epoxy group, an imide bond, an ether bond, an ester bond and an urethane bond. The particular photosensitive resin used for forming the columnar spacers permits the surface of a polyimide alignment film to be prevented from being swollen by or dissolved in a developing solution in the subsequent step so as to maintain the crystal orientation satisfactorily.
    Type: Grant
    Filed: March 15, 1994
    Date of Patent: March 12, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Rei Hasegawa, Miki Mori
  • Patent number: 5453991
    Abstract: A highly-integrated semiconductor IC device includes a semiconductive substrate, on which an internal function circuit is arranged to have a first plurality of input terminals and a second plurality of output terminals. A logic circuit is arranged on the substrate and is connected to the internal circuit through the output terminals. The logic circuit has a third plurality of output terminals, which are less in number than the outputs of the internal circuit. These logic output terminals are coupled to the same number of inspection terminals, which are adapted to be coupled to a known electric inspection tool. The logic circuit processes the voltage signals appearing at the output terminals of the internal circuit so as to cause these signals to decrease in number. The output signals of the logic circuit are sent to the inspection terminals as monitor signals, based on which an inspection is carried out to determine whether the internal circuit operates normally.
    Type: Grant
    Filed: March 15, 1993
    Date of Patent: September 26, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouhei Suzuki, Kouji Suzuki, Miki Mori, Akinori Hongu, Nobuo Iwase
  • Patent number: 5071787
    Abstract: In a semiconductor device including a substrate having a wiring layer formed on its major surface and a semiconductor element having an electrode formed on its major surface in which a face-down bonding is achieved with the major surface of the semiconductor element oppositely facing that major surface of the semiconductor substrate which is located opposite to the electrode on the semiconductor element, first bumps formed of gold are formed on the electrode of the semiconductor element, second bumps formed of an indium/tin alloy are formed on the first bumps and an electrical and mechanical bond is achieved, by the second bumps, between the first bumps and the wiring layer in which case the second bumps are heated to an extent not exceeding the melting point of the second bumps.
    Type: Grant
    Filed: February 9, 1990
    Date of Patent: December 10, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Miki Mori, Masayuki Saito
  • Patent number: 4857482
    Abstract: A support is formed and comprises a base, a resin layer which is formed on the base and on recesses which are formed on a surface of the base, and a conductive layer which is formed on a portion of a surface of the resin layer, other than where the recesses are formed. The surface of the recesses is electrically charged by way of a corona discharge to create static electricity in the recesses. Metal balls to be formed into bump electrodes are held in the recesses by way of the static electricity. Then, each of the metal balls is bonded to a corresponding electrode terminal of an electronic component by hot press unit while the electronic component is opposed to the support.
    Type: Grant
    Filed: June 29, 1988
    Date of Patent: August 15, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Saito, Akira Niitsuma, Hirosi Ohdaira, Chiaki Tanuma, Miki Mori