Abstract: Systems and methods are provided for an equalizer. An equalizer includes a first voltage correcting circuit configured to correct a communication signal by applying a first variable corrective voltage to the communication signal, the first corrective voltage having a voltage level selected according to a first adjustable granularity. A second voltage correcting circuit is configured to further correct the communication signal by applying a second variable corrective voltage to the communication signal, the second corrective voltage having a voltage level selected according to a second adjustable granularity that is different from the first adjustable granularity.

Abstract: A PLL circuit, having a control loop for an input to a VCO including first and second charge pumps eash having an output coupled to the input of the VCO; an RC network having a first resistance and a capacitance and being and RC network coupled to the output of the first charge pump. A second resistance coupled between the output of the first charge pump and the input to the VCO, the valve of the capacitance C being reduced by a factor X, where V VCO = x C ? ? I CP2 ? t + I CP2 ? R2 VVCO=VCO input voltage Icp2 is the current output by the second charge pump R2=second resistance C?=new capacitance value=C*X C=original capacitance value.

Abstract: A PLL circuit, having a control loop for an input to a VCO including first and second charge pumps eash having an output coupled to the input of the VCO; an RC network having a first resistance and a capacitance and being and RC network coupled to the output of the first charge pump. A second resistance coupled between the output of the first charge pump and the input to the VCO, the valve of the capacitance C being reduced by a factor X, where V VCO = x C ? ? I CP2 ? t + I CP2 ? R2 VVCO=VCO input voltage Icp2 is the current output by the second charge pump R2=second resistance C?=new capacitance value=C*X C=original capacitance value.

Abstract: Analog to digital conversion of signals at rates higher than can be accomplished by a monolithic flash analog to digital converter is achieved using multiple flash analog to digital converters operated in a parallel architecture. Sample timing of the multiple converters is skewed by selecting subfrequencies of a control clock or different phases of a control clock as the source for the sample control signal. The multiple flash converter outputs are then digitally recombined to produce a single output identical to a flash converter operating at a higher speed than could be obtained for a given set of circuit parameters.

Abstract: A thermal sensor for use in integrated circuits includes a plurality of MOSFET diodes. The thermal sensor senses temperature within the integrated circuit and provides a control signal. The control signal may be utilized to control thermal management devices such as fans, clock dividers, or other thermal management devices. The thermal sensor is preferably integrated within the microprocessor adjacent clock driver circuitry. The thermal sensor generally includes current mirrors coupled to diodes. The diodes control the output of the current mirrors so that larger current is drawn from the current mirrors when the temperature is higher in the integrated circuit. The current mirrors supply current to a constant signal source and an impedance circuit. The control circuit compares the voltages from the impedance circuit and the constant signal source. The control circuit provides the control signal when the signal from the impedance circuit is above a predetermined threshold.

Abstract: A method and apparatus provide fuse trimming or analog integrated circuit parameters in plastic packages. The apparatus includes an electrically interruptible circuit element, such as a fuse; a level reading unit which reads the state of the electrically interruptible circuit element and generates a code in response to the state; a state altering unit, such as a current source for providing a blow current; and a control circuit. A test level reading device allows screening for marginally-blown fuses. A switchable element removes applied voltage from fuses when the fuse is not being blown or read to prevent fuse regrowth.

Abstract: An apparatus for generating an analog output signal representative of a digital input signal, which digital input signal is received as a plurality of bits. The apparatus includes a current branch array for establishing a plurality of output current branches and a reference current branch. The current branch array includes a first, a second, and a third electrical node. Each respective output current branch is responsive to a respective bit to switchably connect the respective output current branch intermediate the first and the second electrical node when the respective bit is a first state and to switchably connect the respective output current branch intermediate the first and the third electrical node when the respective bit is in a second state. Each respective output current branch and the reference current branch includes a respective switching device which responds to a switching signal to enable current flow through the first electrical node.

Abstract: A method and apparatus provide fuse trimming of analog integrated circuit parameters in plastic packages. The apparatus includes an electrically interruptible circuit element, such as a fuse; a level reading unit which reads the state of the electrically interruptible circuit element and generates a code in response to the state; a state altering unit, such as a current source for providing a blow current; and a control circuit. A test level reading device allows screening for marginally-blown fuses. A switchable element removes applied voltage from fuses when the fuse is not being blown or read to prevent fuse regrowth.

Abstract: A converter circuit provides analog to digital and digital to analog functions on a single silicon device. A flash analog to digital converter produces digital outputs using comparators which each receive an input signal and which each have different reference voltages. A decoder receiving digital inputs activates switches to connect selected ones of the same voltage references used by the flash analog to digital converter to a buffer which produces an analog output. The converter circuit can be a single or multi-stage flash analog to digital converter operating in a single channel or multi-channel environment. Timing and control logic prevents switching from occurring at times when perturbations on the voltage references could affect the analog and digital outputs.

Abstract: There is disclosed a three-state buffer including a comparator circuit which comprises a plurality of bipolar transistors and which generates first and second control voltages which are dependent upon the forward biased base to emitter voltage drops of the transistors. The comparator circuit also includes a threshold circuit establishing a threshold voltage intermediate the first and second control voltages which is also dependent upon the forward biased base to emitter voltage drops of the transistors. As a result, the threshold voltage is always intermediate the first and second control voltages to assure reliable operation of the comparator circuit notwithstanding variations in integrated circuit processing parameters or integrated circuit operating temperatures.

Abstract: There is disclosed a trimming circuit for use in integrated circuits for adjusting a circuit parameter to a desired level. The trimming circuit includes an input terminal and a fuse coupled between the input terminal and a supply voltage. The fuse is convertible from a low resistance condition to an open circuit condition in response to a first voltage potential applied to the input. The trimming circuit also includes circuit means coupled to the input for causing the circuit parameter to be permanently adjusted in response to the fuse being converted to the open circuit condition and is also responsive to a second voltage potential applied to the input for causing the circuit parameter to be temporarily adjusted without the fuse being converted to the open circuit condition.

Abstract: The invention comprises an operational amplifier circuit having a shielded transistor device whose drain is surrounded by a gate comprising an annular ribbon of polysilicon. The gate is connected to a trackable potential that fluctuates but is keyed to a voltage slightly above the average between the positive and negative circuit bias. The shielded transistor device allows the operational amplifier circuit of which it is a part to function at extended voltage levels of 12 volts.

Abstract: There is disclosed an operational amplifier which is arranged for sensing the voltages provided by a plurality of input voltage sources and which diminishes the level of noise at the operational amplifier output resulting from the selection of the input voltage sources. The operational amplifier includes a first amplification stage having first and second voltage sensing intputs, a common input, and an output, and a second amplification stage having an input and an output. Switch means are disposed between the first stage output and the second stage input for selectively coupling the amplified signal at the first stage output resulting from an input signal at the first input to the second stage input or the amplified signal at the first stage output resulting from an input signal at the second input to the second stage input.

Abstract: A dual channel A/D and D/A converter includes a first channel converter, a second channel converter, and a reference generator all formed on a single semiconductor substrate. The reference generator is disposed intermediate the first channel converter and the second channel converter for effecting crosstalk isolation therebetween. The dual channel converter is formed of a unique differential structure having "coaxial" isolation of bus lines and interconnections, thereby achieving a higher degree of unwanted channel-to-channel crosstalk.