Abstract: A central control circuit in a semiconductor memory device includes a command decoder and an MRS output circuit. The command decoder decodes an internal control signal. The MRS output circuit generates a control signal for writing a set value of a mode register into a memory cell. According to the control signal, the set value of the mode register is transferred to a data input/output line. A data input/output buffer receives data from the data input/output line, and the data is written into a specific memory cell. The written data is output at a data input/output pin by a normal read operation. A semiconductor memory device allowing externally monitoring a set value of a mode register is thus provided.

Abstract: One of the two data input/output line pairs and the selected bit line pair included in a memory cell array are connected by a column switch, and the read out data is output to a preamplifier through a switching circuit. A data input/output line pair of the data input/output line pairs which is not used for data transmission is equalized by an equalizing circuit. Therefore, data readout and equalizing operation are carried out in parallel, thereby achieving high-speed data readout.