Abstract: An electronic component that includes: a base body; wiring inside the base body; a glass film covering an outer surface of the base body; an underlying electrode electrically connected to the wiring and covering a part of the glass film; and a metal layer covering the underlying electrode, wherein the glass film includes an uncovered portion that is not covered with the underlying electrode and separated from an outer edge of the underlying electrode by more than 10 ?m, and a boundary portion that is not covered with the underlying electrode and not separated from the outer edge of the underlying electrode by more than 10 ?m, and a thickness of the boundary portion is larger than a thickness of the uncovered portion.

Abstract: An electronic component that includes: a base body having an outer surface defining a recess with an inner surface, wherein, when the recess is viewed in a direction orthogonal to the outer surface, at least a part of an outer edge of the recess is curved, and when the recess is viewed in a section orthogonal to the outer surface, at least a part of the inner surface of the recess is curved; a wiring inside the base body; and a glass film covering the outer surface of the base body and not covering the inner surface of the recess.

Abstract: An electronic component includes a ceramic body, and an external electrode on the ceramic body, the external electrode includes a base layer continuously covering an end surface of the ceramic body and a portion of a side surface bordering the end surface, and a plating layer covering the base layer, the ceramic body includes a recess open on the side surface, an opening of the recess includes a pair of edges, one edge of the opening is located within a covered region on the side surface covered with the base layer, and the other edge of the opening is spaced away from the covered region.

Abstract: An electronic component that includes: an element body; and an insulating film covering an outer surface of the element body. The insulating film has a mix layer and a glass layer. The mix layer has a first glass and powder particles. The glass layer contains a second glass and has a smaller content percentage of the powder particles than the mix layer. The mix layer is on a side of the insulating film closer to the element body when viewed from the glass layer.

Abstract: An electronic component that includes: an element body; and an insulating film covering an outer surface of the element body. The element body has a crack that opens to the outer surface. In a cross section orthogonal to the outer surface, the crack has a first portion that extends from the opening and intersects an axis orthogonal to the outer surface. In addition, one portion of the insulating film penetrates into at least an inner space of the first portion of the crack.

Abstract: An electronic component that includes: a base body; and an insulating film covering an outer surface of the base body. The insulating film includes the film main body and a plurality of the thick film portions. A material of the film main body includes a glass. A material of the thick film portion is the same as the glass of the film main body. A thickness of the thick film portion is larger than an average thickness of the film main body.

Abstract: In manufacturing a semiconductor memory, a gate oxide film, a polysilicon film and a WSi film are laminated on the major surface of a semiconductor wafer corresponding to both an element region on which a semiconductor chip is to be formed and a dicing region serving as a dicing line. These laminated films are patterned to form a projected dummy pattern having substantially the same wiring structure as that of a gate electrode portion of a selective transistor. The dummy pattern is formed between element isolation regions along a dicing direction at the same time when the gate electrode portion is formed. The dummy pattern prevents stress caused by dicing from being concentrated on an insulation film in the dicing region, thereby minimizing a crack waste. Consequently, in the semiconductor memory, a malfunction due to a large crack waste caused by the dicing, can be avoided.

Abstract: A translation evaluation apparatus is includes: a parallel translation corpus data base (310) that stores, in an associated manner, base original texts and respective model translated texts of the base original texts, a parallel translation linking unit (225) that links the model translated texts to create a linked model translated text, and links the base original texts that are associated with the model translated texts that form the linked model translated text to create a linked original text; an evaluation target translated text input unit (110) that is used to input evaluation target translated text and that corresponds with the base original text; and an evaluation value computation unit (235) that links the evaluation target translated text to create a linked evaluation target translated text, and compares the linked evaluation target translated text and the linked model translated text to evaluate the translation quality of the evaluation target translated text.

Abstract: In manufacturing a semiconductor memory, a gate oxide film, a polysilicon film and a WSi film are laminated on the major surface of a semiconductor wafer corresponding to both an element region on which a semiconductor chip is to be formed and a dicing region serving as a dicing line. These laminated films are patterned to form a projected dummy pattern having substantially the same wiring structure as that of a gate electrode portion of a selective transistor. The dummy pattern is formed between element isolation regions along a dicing direction at the same time when the gate electrode portion is formed. The dummy pattern prevents stress caused by dicing from being concentrated on an insulation film in the dicing region, thereby minimizing a crack waste. Consequently, in the semiconductor memory, a malfunction due to a large crack waste caused by the dicing, can be avoided.

Abstract: In manufacturing a semiconductor memory, a gate oxide film, a polysilicon film and a WSi film are laminated on the major surface of a semiconductor wafer corresponding to both an element region on which a semiconductor chip is to be formed and a dicing region serving as a dicing line. These laminated films are patterned to form a projected dummy pattern having substantially the same wiring structure as that of a gate electrode portion of a selective transistor. The dummy pattern is formed between element isolation regions along a dicing direction at the same time when the gate electrode portion is formed. The dummy pattern prevents stress caused by dicing from being concentrated on an insulation film in the dicing region, thereby minimizing a crack waste. Consequently, in the semiconductor memory, a malfunction due to a large crack waste caused by the dicing, can be avoided.

Abstract: The present invention provides an apparatus and method for natural language processing capable of providing an appropriate result of natural language processing. More specifically, the present invention provides a natural language processing apparatus for achieving a syntax analysis and/or a syntax generation by using natural language patterns with, at least, pattern name and pattern component. The natural language processing apparatus comprises dictionary reference means for picking up one or more natural language patterns applicable for the syntax analysis and/or the syntax generation among the natural language patterns prepared in a pattern dictionary in advance, pattern inspection means for inspecting whether the applicable natural language patterns meet a tree structure or not, and pattern application means for applying the natural language patterns to the tree structure if the natural language patterns meet the tree structure.

Abstract: In manufacturing a semiconductor memory, a gate oxide film, a polysilicon film and a WSi film are laminated on the major surface of a semiconductor wafer corresponding to both an element region on which a semiconductor chip is to be formed and a dicing region serving as a dicing line. These laminated films are patterned to form a projected dummy pattern having substantially the same wiring structure as that of a gate electrode portion of a selective transistor. The dummy pattern is formed between element isolation regions along a dicing direction at the same time when the gate electrode portion is formed. The dummy pattern prevents stress caused by dicing from being concentrated on an insulation film in the dicing region, thereby minimizing a crack waste. Consequently, in the semiconductor memory, a malfunction due to a large crack waste caused by the dicing, can be avoided.

Abstract: A semiconductor device includes a dicing region provided on a semiconductor substrate to separate a plurality of semiconductor chips each having a gate portion from each other. The semiconductor device further includes a plurality of element isolation regions provided on a surface portion of the semiconductor substrate within the dicing region, a plurality of first dummy patterns formed on a surface of the semiconductor substrate so as to correspond to intervals of the plurality of element isolation regions, respectively, and a plurality of second dummy patterns formed above the semiconductor substrate within the dicing region so as to correspond to the plurality of first dummy patterns, respectively.

Abstract: In order to realize a numerical information retrieving device which permits a user to retrieve numerical information without caring about representations or unit systems, the numerical information retrieving device of the present invention comprises input means for inputting any document to-be-retrieved or any numerical expression to-be-retrieved; an attribute information dictionary which stores therein attribute names indicative of attributes and conditions for bestowing the attributes, attribute bestowal means for bestowing an attribute on the inputted document or numerical expression by referring to the attribute information dictionary, a conversion information dictionary which stores attribute names indicative of attributes, non-converted character strings and converted character strings therein, and numerical conversion means for converting a numerical representation of a part of the document or numerical expression as is endowed with the attribute, from a non-converted character string into a converted

Abstract: In order to realize a numerical expression retrieving device which permits a user to retrieve a numerical expression without caring about a case where the numerical expression is shortened to a prefix only, the numerical expression retrieving device of the present invention comprises input means for inputting any document to-be-retrieved or any numerical expression to-be-retrieved; syntactic parsing means for parsing the syntactic structure of the inputted document or numerical expression; an attribute dictionary which stores attribute information and unit system information therein, the attribute information including attribute names indicative of attributes, attribute contents indicative of the meanings of the attributes, and basic units for supplementing omitted representations, the unit system information including prefixes for deciding the incomplete or shortened numerical expressions, and multiples indicative of the meanings of the prefixes; a co-occurrence word dictionary which stores therein informati

Abstract: In manufacturing a semiconductor memory, a gate oxide film, a polysilicon film and a WSi film are laminated on the major surface of a semiconductor wafer corresponding to both an element region on which a semiconductor chip is to be formed and a dicing region serving as a dicing line. These laminated films are patterned to form a projected dummy pattern having substantially the same wiring structure as that of a gate electrode portion of a selective transistor. The dummy pattern is formed between element isolation regions along a dicing direction at the same time when the gate electrode portion is formed. The dummy pattern prevents stress caused by dicing from being concentrated on an insulation film in the dicing region, thereby minimizing a crack waste. Consequently, in the semiconductor memory, a malfunction due to a large crack waste caused by the dicing, can be avoided.

Abstract: The present invention provides an apparatus and method for natural language processing capable of providing an appropriate result of natural language processing. More specifically, the present invention provides a natural language processing apparatus for achieving a syntax analysis and/or a syntax generation by using natural language patterns with, at least, pattern name and pattern component. The natural language processing apparatus comprises dictionary reference means for picking up one or more natural language patterns applicable for the syntax analysis and/or the syntax generation among the natural language patterns prepared in a pattern dictionary in advance, pattern inspection means for inspecting whether the applicable natural language patterns meet a tree structure or not, and pattern application means for applying the natural language patterns to the tree structure if the natural language patterns meet the tree structure.