Patents by Inventor Miki Takagi
Miki Takagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8315846Abstract: A design data merging apparatus includes a merging determining unit that determines, for a plurality of design data of which each has product name information and has a same identifier for uniquely identifying a product, whether the product name information given to the plurality of design data are the same, and a merged data creating unit that merges the plurality of design data when it is determined by the merging determining unit that the product name information given to the plurality of design data are the same, and creates merged data obtained by merging a plurality of design data.Type: GrantFiled: April 12, 2010Date of Patent: November 20, 2012Assignee: Fujitsu LimitedInventors: Takeo Nakamura, Miki Takagi, Junko Taira
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Publication number: 20120254819Abstract: The disclosed method includes: generating data of a first circuit diagram by disposing a block that represents a connection relationship between first branch lines included in a first bus line in a second circuit diagram and second branch lines included in a second bus line to be connected to the first bus line in the second circuit diagram so as to connect the first bus line with the second bus line through the block, wherein the block represents that the connection relationship identified by connection relationship data is depicted in detail in a lower-layer than a layer of the block; and generating display data including the connection relationship data and the first circuit diagram to output the generated display data.Type: ApplicationFiled: March 22, 2012Publication date: October 4, 2012Applicant: FUJITSU LIMITEDInventor: Miki TAKAGI
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Publication number: 20100262270Abstract: A design data merging apparatus includes a merging determining unit that determines, for a plurality of design data of which each has product name information and has a same identifier for uniquely identifying a product, whether the product name information given to the plurality of design data are the same, and a merged data creating unit that merges the plurality of design data when it is determined by the merging determining unit that the product name information given to the plurality of design data are the same, and creates merged data obtained by merging a plurality of design data.Type: ApplicationFiled: April 12, 2010Publication date: October 14, 2010Applicant: FUJITSU LIMITEDInventors: Takeo Nakamura, Miki Takagi, Junko Taira
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Publication number: 20090249058Abstract: A system aiding for design includes a determining unit determining whether it is possible to first product data with second product data by comparing interface data of the first product data with interface data of the second product data and a replacing unit replacing the first product data contained in design data with the second product data when the determining unit determines that replacement is possible.Type: ApplicationFiled: March 26, 2009Publication date: October 1, 2009Applicant: FUJITSU LIMITEDInventors: Junko TAIRA, Miki Takagi, Yoshitomo Kumagai
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Publication number: 20090240836Abstract: The configuration data obtaining unit obtains a network configuration data, and the actual-apparatus collection result data obtaining unit obtains an actual-apparatus collection result data. Then, the comparing unit compares a network address in the network configuration data corresponding to a network apparatus with a network address in the actual-apparatus collection result data corresponding to the network apparatus, and determines whether the network address is normally set to the network apparatus based on the comparison result.Type: ApplicationFiled: March 18, 2009Publication date: September 24, 2009Applicant: FUJITSU LIMITEDInventors: Miki TAKAGI, Takeo Nakamura, Toshiya Yamazaki
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Patent number: 7337414Abstract: The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones.Type: GrantFiled: April 6, 2006Date of Patent: February 26, 2008Assignee: Fujitsu LimitedInventors: Terunobu Maruyama, Hiroji Takeyama, Takeo Nakamura, Mitsuru Satou, Yuki Kumon, Miki Takagi
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Patent number: 7143375Abstract: The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones.Type: GrantFiled: November 12, 2003Date of Patent: November 28, 2006Assignee: Fujitsu LimitedInventors: Terunobu Maruyama, Hiroji Takeyama, Takeo Nakamura, Mitsuru Satou, Yuki Kumon, Miki Takagi
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Publication number: 20060184903Abstract: The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones.Type: ApplicationFiled: April 6, 2006Publication date: August 17, 2006Applicant: Fujitsu LimitedInventors: Terunobu Maruyama, Hiroji Takeyama, Takeo Nakamura, Mitsuru Satou, Yuki Kumon, Miki Takagi
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Patent number: 7086016Abstract: A method for verifying a logical equivalency between two logic circuits having different combinational logic circuits includes the steps of converting into a logic circuit a logic cone that has been determined for each of the two logic circuits, the logic cone including all inputs and all logic circuits which affect one output of the combinational logic circuit, storing a logical expression converted by the converting step and a logic circuit element included in the logic cone while correlating the logical expression with the logic circuit element, and specifying the logic circuit element corresponding to a specified term in the logical expression that has been converted.Type: GrantFiled: June 4, 2003Date of Patent: August 1, 2006Assignee: Fujitsu LimitedInventors: Kazuhiro Matsuzaki, Hiroji Takeyama, Miki Takagi, Hiroshi Noguchi
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Publication number: 20060047451Abstract: A circuit diagram display apparatus displays a plurality of logic circuit diagrams. An associating unit associates the logic circuits based on at least any one of identification information, structural information, logical equivalence information, and external designated information about the logic circuits. A display format changing unit changes a display format between a side-by-side format and one-below-the-other format. A display controller performs control to display a target point in the logic circuit diagram in the same position before and after the display format is changed.Type: ApplicationFiled: December 28, 2004Publication date: March 2, 2006Applicant: FUJITSU LIMITEDInventors: Mituru Sato, Yuki Kumon, Hiroji Takeyama, Terunobu Maruyama, Miki Takagi, Tomoki Kanemochi
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Publication number: 20040098683Abstract: The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones.Type: ApplicationFiled: November 12, 2003Publication date: May 20, 2004Applicant: FUJITSU LIMITEDInventors: Terunobu Maruyama, Hiroji Takeyama, Takeo Nakamura, Mitsuru Satou, Yuki Kumon, Miki Takagi
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Patent number: 6678871Abstract: A circuit designing apparatus includes a circuit information database to store information regarding a circuit, an automatic designing processing section to read out the information regarding the circuit from the circuit information database and designing the circuit for each predetermined unit to be processed, and a design information database to store design information obtained by the automatic designing processing section and including peculiarizing information of circuit elements, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit. The circuit designing apparatus allows a desired circuit to be automatically produced, regenerated or optimized.Type: GrantFiled: September 9, 2002Date of Patent: January 13, 2004Assignee: Fujitsu LimitedInventors: Hiroji Takeyama, Koichi Itaya, Miki Takagi, Takehiro Yamazaki
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Publication number: 20030237065Abstract: A method for verifying a logical equivalency between two logic circuits having different combinational logic circuits includes the steps of converting into a logic circuit a logic cone that has been determined for each of the two logic circuits, the logic cone including all inputs and all logic circuits which affect one output of the combinational logic circuit, storing a logical expression converted by the converting step and a logic circuit element included in the logic cone while correlating the logical expression with the logic circuit element, and specifying the logic circuit element corresponding to a specified term in the logical expression that has been converted.Type: ApplicationFiled: June 4, 2003Publication date: December 25, 2003Applicant: FUJITSU LIMITEDInventors: Kazuhiro Matsuzaki, Hiroji Takeyama, Miki Takagi, Hiroshi Noguchi
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Patent number: 6618834Abstract: A circuit designing apparatus includes a circuit information database to store information regarding a circuit, an automatic designing processing section to read out the information regarding the circuit from the circuit information database and designing the circuit for each predetermined unit to be processed, and a design information database to store design information obtained by the automatic designing processing section and including peculiarizing information of circuit elements, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit. The circuit designing apparatus allows a desired circuit to be automatically produced, regenerated or optimized.Type: GrantFiled: March 30, 2001Date of Patent: September 9, 2003Assignee: Fujitsu LimitedInventors: Hiroji Takeyama, Koichi Itaya, Miki Takagi, Takehiro Yamazaki
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Publication number: 20030033595Abstract: An apparatus is provided for automatically modifying serious semantic grammar errors in an HDL description and to clearly show the modified portions. For these purposes, the apparatus includes: means for detecting a portion in which variables on the right and the left sides of an assignment statement are inconsistent in type; a template for converting the type of the variable on the right side of the assignment statement into that of the variable on the left side; means for modifying the portion into a correct description by applying the type conversion function to the right side of the assignment statement having the portion; and means for attaching a comment about the modification to the modified portion, and is used to automatically modify inappropriate descriptions in the design information of an electronic system or of a logic circuit described in a hardware description language such as VHDL and Verilog-HDL.Type: ApplicationFiled: November 13, 2001Publication date: February 13, 2003Applicant: Fujitsu LimitedInventors: Miki Takagi, Hiroji Takeyama, Hiroshi Noguchi
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Publication number: 20030009727Abstract: The invention provides a circuit designing apparatus which includes a circuit information database for storing information regarding a circuit, an automatic designing processing section for reading out the information regarding the circuit from the circuit information database and designing the circuit for each predetermined unit to be processed, and a design information database for storing design information obtained by the automatic designing processing section and including peculiarizing information of circuit elements, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit. The circuit designing apparatus allows a desired circuit to be automatically produced, regenerated or optimized.Type: ApplicationFiled: September 9, 2002Publication date: January 9, 2003Applicant: FUJITSU LIMITEDInventors: Hiroji Takeyama, Koichi Itaya, Miki Takagi, Takehiro Yamazaki
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Publication number: 20020083398Abstract: The invention provides a circuit designing apparatus which includes a circuit information database for storing information regarding a circuit, an automatic designing processing section for reading out the information regarding the circuit from the circuit information database and designing the circuit for each predetermined unit to be processed, and a design information database for storing design information obtained by the automatic designing processing section and including peculiarizing information of circuit elements, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit. The circuit designing apparatus allows a desired circuit to be automatically produced, regenerated or optimized.Type: ApplicationFiled: March 30, 2001Publication date: June 27, 2002Inventors: Hiroji Takeyama, Koichi Itaya, Miki Takagi, Takehiro Yamazaki
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Patent number: 6240541Abstract: A circuit designing apparatus of an interactive type which enables a simplified and highspeed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.Type: GrantFiled: January 11, 1999Date of Patent: May 29, 2001Assignee: Fujitsu LimitedInventors: Mitsuru Yasuda, Hiroyuki Sugiyama, Noriyuki Ito, Ryoichi Yamashita, Tadashi Konno, Yasunori Abe, Naomi Bizen, Terunobu Maruyama, Yoshiyuki Kato, Tomoyuki Isomura, Hiroshi Ikeda, Miki Takagi
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Patent number: 5889677Abstract: A circuit designing apparatus of an interactive type which enables a simplified and high-speed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.Type: GrantFiled: December 19, 1995Date of Patent: March 30, 1999Assignee: Fujitsu LimitedInventors: Mitsuru Yasuda, Hiroyuki Sugiyama, Noriyuki Ito, Ryoichi Yamashita, Tadashi Konno, Yasunori Abe, Naomi Bizen, Terunobu Maruyama, Yoshiyuki Kato, Tomoyuki Isomura, Hiroshi Ikeda, Miki Takagi