Patents by Inventor Miki Yumoto

Miki Yumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11658235
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first region, and a first insulating layer. The first electrode includes a first electrode portion. The first region contains Ga and N. The first region includes a first subregion, a second subregion, and a third subregion. The first subregion and the third subregion contain at least one first element selected from the group consisting of Ar, B, P, N, and Fe. The first subregion is located between the first electrode portion and the second subregion in a first direction. The second subregion does not contain the first element, or concentration of the first element in the second subregion is lower than concentration of the first element in the first subregion and lower than concentration of the first element in the third subregion. The first insulating layer is provided between the first electrode and the first region.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: May 23, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Kuraguchi, Yosuke Kajiwara, Miki Yumoto, Hiroshi Ono
  • Patent number: 10784361
    Abstract: A semiconductor device according to an embodiment includes a first GaN-based semiconductor layer, a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer and having a wider band gap than the first GaN-based semiconductor layer, a source electrode electrically connected to the second GaN-based semiconductor layer, a drain electrode electrically connected to the second GaN-based semiconductor layer, a gate electrode provided between the source electrode and the drain electrode, and a passivation film provided on the second GaN-based semiconductor layer between the source electrode and the gate electrode and between the gate electrode and the drain electrode, the passivation film including a first insulating film and a second insulating film, the first insulating film including nitrogen, the first insulating film having a thickness equal to or greater than 0.2 nm and less than 2 nm, the second insulating film including oxygen and provided on the first insulating film.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: September 22, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Saito, Miki Yumoto
  • Patent number: 10373833
    Abstract: A semiconductor device of an embodiment includes a first GaN-based semiconductor layer, a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer and having a larger bandgap than the first GaN-based semiconductor layer, a source electrode provided on the second GaN-based semiconductor layer, a drain electrode provided on the second GaN-based semiconductor layer, a recess provided between the source electrode and the drain electrode in the second GaN-based semiconductor layer, a gate insulating film provided on a surface of the recess, and a gate electrode provided on the gate insulating film and having an end portion in a gate width direction, located in the recess.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: August 6, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Aya Shindome, Masahiko Kuraguchi, Hisashi Saito, Shigeto Fukatsu, Miki Yumoto, Yosuke Kajiwara
  • Publication number: 20190088771
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first region, and a first insulating layer. The first electrode includes a first electrode portion. The first region contains Ga and N. The first region includes a first subregion, a second subregion, and a third subregion. The first subregion and the third subregion contain at least one first element selected from the group consisting of Ar, B, P, N, and Fe. The first subregion is located between the first electrode portion and the second subregion in a first direction. The second subregion does not contain the first element, or concentration of the first element in the second subregion is lower than concentration of the first element in the first subregion and lower than concentration of the first element in the third subregion. The first insulating layer is provided between the first electrode and the first region.
    Type: Application
    Filed: February 21, 2018
    Publication date: March 21, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Kuraguchi, Yosuke Kajiwara, Miki Yumoto, Hiroshi Ono
  • Patent number: 10186588
    Abstract: According to one embodiment, a semiconductor substrate includes a first semiconductor layer including Alx1Ga1-x1N (0<x1?1) and including carbon and oxygen, and a second semiconductor layer including Alx2Ga1-x2N (0<x2<x1) and including carbon and oxygen. A second ratio of a carbon concentration of the second semiconductor layer to an oxygen concentration of the second semiconductor layer is 730 or more.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: January 22, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daimotsu Kato, Hisashi Yoshida, Jumpei Tajima, Kenjiro Uesugi, Toshiki Hikosaka, Miki Yumoto, Shinya Nunoue, Masahiko Kuraguchi
  • Patent number: 10141439
    Abstract: A semiconductor device according to an embodiment includes a first GaN based semiconductor layer of a first conductive type, a second GaN based semiconductor layer of the first conductive type provided above the first GaN based semiconductor layer, a third GaN based semiconductor layer of a second conductive type provided above a part of the second GaN based semiconductor layer, a epitaxially grown fourth GaN based semiconductor layer of the first conductive type provided above the third GaN based semiconductor layer, a gate insulating film provided on the second, third, and fourth GaN based semiconductor layer, a gate electrode provided on the gate insulating film, a first electrode provided on the fourth GaN based semiconductor layer, a second electrode provided at the side of the first GaN based semiconductor layer opposite to the second GaN based semiconductor layer, and a third electrode provided on the second GaN based semiconductor layer.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: November 27, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Miki Yumoto, Masahiko Kuraguchi
  • Publication number: 20170148908
    Abstract: A semiconductor device according to an embodiment includes a first GaN based semiconductor layer of a first conductive type, a second GaN based semiconductor layer of the first conductive type provided above the first GaN based semiconductor layer, a third GaN based semiconductor layer of a second conductive type provided above a part of the second GaN based semiconductor layer, a epitaxially grown fourth GaN based semiconductor layer of the first conductive type provided above the third GaN based semiconductor layer, a gate insulating film provided on the second, third, and fourth GaN based semiconductor layer, a gate electrode provided on the gate insulating film, a first electrode provided on the fourth GaN based semiconductor layer, a second electrode provided at the side of the first GaN based semiconductor layer opposite to the second GaN based semiconductor layer, and a third electrode provided on the second GaN based semiconductor layer.
    Type: Application
    Filed: February 3, 2017
    Publication date: May 25, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Miki YUMOTO, Masahiko KURAGUCHI
  • Patent number: 9620599
    Abstract: A semiconductor device according an embodiment includes a GaN layer, a GaN-based semiconductor layer provided on the GaN layer and having a wider band gap than the GaN layer, a source electrode electrically connected to the GaN-based semiconductor layer, a drain electrode electrically connected to the GaN-based semiconductor layer, a gate electrode provided in the GaN-based semiconductor layer between the source electrode and the drain electrode, and a gate insulating film provided at least between the GaN layer and the gate electrode, the gate insulating film including a first insulating film and a second insulating film, the first insulating film provided on the GaN layer, the first insulating film having a thickness equal to or greater than 0.2 nm and less than 2 nm, the first insulating film including nitrogen, the second insulating film provided between the first insulating film and the gate electrode, the second insulating film including oxygen.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: April 11, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Saito, Miki Yumoto
  • Publication number: 20160284831
    Abstract: A semiconductor device of an embodiment includes a first GaN-based semiconductor layer, a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer and having a larger bandgap than the first GaN-based semiconductor layer, a source electrode provided on the second GaN-based semiconductor layer, a drain electrode provided on the second GaN-based semiconductor layer, a recess provided between the source electrode and the drain electrode in the second GaN-based semiconductor layer, a gate insulating film provided on a surface of the recess, and a gate electrode provided on the gate insulating film and having an end portion in a gate width direction, located in the recess.
    Type: Application
    Filed: February 29, 2016
    Publication date: September 29, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Aya SHINDOME, Masahiko KURAGUCHI, Hisashi SAITO, Shigeto FUKATSU, Miki YUMOTO, Yosuke KAJIWARA
  • Patent number: 9412825
    Abstract: A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takaaki Yasumoto, Naoko Yanase, Kazuhide Abe, Takeshi Uchihara, Yasunobu Saito, Toshiyuki Naka, Akira Yoshioka, Tasuku Ono, Tetsuya Ohno, Hidetoshi Fujimoto, Shingo Masuko, Masaru Furukawa, Yasunari Yagi, Miki Yumoto, Atsuko Iida, Yukako Murakami, Takako Motai
  • Publication number: 20160225857
    Abstract: A semiconductor device according an embodiment includes a GaN layer, a GaN-based semiconductor layer provided on the GaN layer and having a wider band gap than the GaN layer, a source electrode electrically connected to the GaN-based semiconductor layer, a drain electrode electrically connected to the GaN-based semiconductor layer, a gate electrode provided in the GaN-based semiconductor layer between the source electrode and the drain electrode, and a gate insulating film provided at least between the GaN layer and the gate electrode, the gate insulating film including a first insulating film and a second insulating film, the first insulating film provided on the GaN layer, the first insulating film having a thickness equal to or greater than 0.2 nm and less than 2 nm, the first insulating film including nitrogen, the second insulating film provided between the first insulating film and the gate electrode, the second insulating film including oxygen.
    Type: Application
    Filed: December 16, 2015
    Publication date: August 4, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisashi SAITO, Miki YUMOTO
  • Publication number: 20160225886
    Abstract: A semiconductor device according to an embodiment includes a first GaN-based semiconductor layer, a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer and having a wider band gap than the first GaN-based semiconductor layer, a source electrode electrically connected to the second GaN-based semiconductor layer, a drain electrode electrically connected to the second GaN-based semiconductor layer, a gate electrode provided between the source electrode and the drain electrode, and a passivation film provided on the second GaN-based semiconductor layer between the source electrode and the gate electrode and between the gate electrode and the drain electrode, the passivation film including a first insulating film and a second insulating film, the first insulating film including nitrogen, the first insulating film having a thickness equal to or greater than 0.2 nm and less than 2 nm, the second insulating film including oxygen and provided on the first insulating film.
    Type: Application
    Filed: January 12, 2016
    Publication date: August 4, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisashi SAITO, Miki YUMOTO
  • Patent number: 9337300
    Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer, a gate electrode provided above the nitride semiconductor layer, a source electrode provided above the nitride semiconductor layer, a drain electrode provided above the nitride semiconductor layer at a side opposite to the source electrode with respect to the gate electrode, a first silicon nitride film provided above the nitride semiconductor layer between the drain electrode and the gate electrode, and a second silicon nitride film provided between the nitride semiconductor layer and the gate electrode, an atomic ratio of silicon to nitrogen in the second silicon nitride film being lower than an atomic ratio of silicon to nitrogen in the first silicon nitride film.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: May 10, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Kuraguchi, Akira Yoshioka, Miki Yumoto, Hisashi Saito, Kohei Oasa, Toru Sugiyama
  • Publication number: 20160079410
    Abstract: A semiconductor device includes a first electrode, a second electrode, a third electrode, and a nitride semiconductor layer. The first electrode has a first surface. The second electrode has a second surface. The second surface is provided with a plurality of convex portions and concave portions. The second electrode is spaced from the first electrode in a first direction. The third electrode is spaced from the first electrode in a second direction intersecting the first direction. The nitride semiconductor layer is provided between the first surface and the second surface, and between the third electrode and the second surface.
    Type: Application
    Filed: March 3, 2015
    Publication date: March 17, 2016
    Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Hidetoshi FUJIMOTO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI
  • Patent number: 9276099
    Abstract: A semiconductor device of one embodiment, including the semiconductor layer including a III-V group nitride semiconductor; a groove portion formed in the semiconductor layer; the gate insulating film formed at least on a bottom surface of the groove portion, the gate insulating film being a stacked film of a first insulating film and a second insulating film of which dielectric constant is higher than that of the first insulating film; the gate electrode formed on the gate insulating film; and a source electrode and a drain electrode formed on the semiconductor layer across the gate electrode, in which the second insulating film is selectively formed only under the gate electrode.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: March 1, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Miki Yumoto, Masahiko Kuraguchi
  • Patent number: 9224818
    Abstract: A semiconductor device of an embodiment includes a semiconductor layer formed of a III-V group nitride semiconductor, a first silicon nitride film formed on the semiconductor layer, a gate electrode formed on the first silicon nitride film, a source electrode and a drain electrode formed on the semiconductor layer such that the gate electrode is interposed between the source electrode and the drain electrode, and a second silicon nitride film formed between the source electrode and the gate electrode and between the drain electrode and the gate electrode and having an oxygen atom density lower than that of the first silicon nitride film.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: December 29, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Miki Yumoto
  • Patent number: 9224819
    Abstract: A semiconductor device of an embodiment includes a semiconductor layer formed of a III-V group nitride semiconductor, a first silicon nitride film formed on the semiconductor layer, a gate electrode formed on the first silicon nitride film, a source electrode and a drain electrode formed on the semiconductor layer such that the gate electrode is interposed between the source electrode and the drain electrode, and a second silicon nitride film formed between the source electrode and the gate electrode and between the drain electrode and the gate electrode and having an oxygen atom density lower than that of the first silicon nitride film.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: December 29, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Miki Yumoto
  • Publication number: 20150263700
    Abstract: According to one embodiment, a semiconductor device includes a GaN-based semiconductor layer, a resonator that uses a first portion of the GaN-based semiconductor layer as a piezoelectric layer to resonate, and a transistor that uses a second portion of the GaN-based semiconductor layer as a channel layer.
    Type: Application
    Filed: September 2, 2014
    Publication date: September 17, 2015
    Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Toshiyuki NAKA, Akira YOSHIOKA, Tasuku ONO, Tetsuya OHNO, Hidetoshi FUJIMOTO, Shingo MASUKO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI, Yoshikazu SUZUKI
  • Publication number: 20150263152
    Abstract: A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.
    Type: Application
    Filed: August 29, 2014
    Publication date: September 17, 2015
    Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Toshiyuki NAKA, Akira YOSHIOKA, Tasuku ONO, Tetsuya OHNO, Hidetoshi FUJIMOTO, Shingo MASUKO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI, Takako MOTAI
  • Publication number: 20150263101
    Abstract: In one embodiment, a semiconductor device includes a semiconductor chip including a nitride semiconductor layer, and including a control electrode, a first electrode and a second electrode provided on the nitride semiconductor layer. The device further includes a support including a substrate, and including a control terminal, a first terminal and a second terminal provided on the substrate. The semiconductor chip is provided on the support such that the control electrode, the first electrode and the second electrode face the support. The control electrode, the first electrode and the second electrode of the semiconductor chip are electrically connected to the control terminal, the first terminal and the second terminal of the support, respectively.
    Type: Application
    Filed: September 10, 2014
    Publication date: September 17, 2015
    Inventors: Shingo Masuko, Takaaki Yasumoto, Naoko Yanase, Miki Yumoto, Masahito Mimura, Yasunobu Saito, Akira Yoshioka, Hidetoshi Fujimoto, Takeshi Uchihara, Tetsuya Ohno, Toshiyuki Naka, Tasuku Ono