Abstract: The first input circuit detects an input signal to output a first output signal having the same phase as the input signal. The second input circuit is configured to detect a first strobe signal to output a second output signal. The third input circuit is configured to detect a second strobe signal as a reversed signal of the first strobe signal to output a third output signal. A data latch circuit includes a first latch circuit and a second latch circuit. It is configured to latch the first output signal in either one of the first latch circuit or the second latch circuit according to the first output signal, the second output signal and the third output signal. It also allows the other one of the first latch circuit or the second latch circuit to input the first output signal thereto.

Abstract: The first input circuit detects an input signal to output a first output signal having the same phase as the input signal. The second input circuit is configured to detect a first strobe signal to output a second output signal. The third input circuit is configured to detect a second strobe signal as a reversed signal of the first strobe signal to output a third output signal. A data latch circuit includes a first latch circuit and a second latch circuit. It is configured to latch the first output signal in either one of the first latch circuit or the second latch circuit according to the first output signal, the second output signal and the third output signal. It also allows the other one of the first latch circuit or the second latch circuit to input the first output signal thereto.

Abstract: A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix, a read unit which reads out data from the memory cells in the memory cell array, a write unit which writes data in the memory cells in the memory cell array, a read voltage generating unit which generates a read voltage and supplies the read voltage to the read unit, and a voltage control unit which controls the read voltage in accordance with temperatures.

Abstract: A semiconductor memory device in accordance with an embodiment comprises a memory cell array and an erase voltage generating circuit. The memory cell array is configured as an arrangement of nonvolatile memory cells. The erase voltage generating circuit is configured to generate an erase voltage for performing data erase of the memory cell array. The erase voltage generating circuit is configured to set, in a data erase mode where the erase voltage is applied to a selected region of the memory cell array in a plurality of erase cycles, a rise waveform of the erase voltage in an initial stage of the plurality of erase cycles to be less steep than a rise waveform of the erase voltage in subsequent cycles.

Abstract: A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix, a read unit which reads out data from the memory cells in the memory cell array, a write unit which writes data in the memory cells in the memory cell array, a read voltage generating unit which generates a read voltage and supplies the read voltage to the read unit, and a voltage control unit which controls the read voltage in accordance with temperatures.

Abstract: A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix, a read unit which reads out data from the memory cells in the memory cell array, a write unit which writes data in the memory cells in the memory cell array, a read voltage generating unit which generates a read voltage and supplies the read voltage to the read unit, and a voltage control unit which controls the read voltage in accordance with temperatures.

Abstract: An aspect of the semiconductor device comprising a package substrate which has a plurality of pads to which a power supply voltage is applied on an upper surface thereof, a first memory chip which is arranged on the package substrate and has a first power supply pad provided on a first side and a second power supply pad provided on a second side perpendicular to the first side, and a second memory chip which is translated in a direction along which the first and second power supply pads of the first memory chip are exposed, arranged on the first memory chip, and has the same structure as the first memory chip, wherein the first and second power supply pads are provided at diagonal corners of the first memory chip, respectively.

Abstract: A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix, a read unit which reads out data from the memory cells in the memory cell array, a write unit which writes data in the memory cells in the memory cell array, a read voltage generating unit which generates a read voltage and supplies the read voltage to the read unit, and a voltage control unit which controls the read voltage in accordance with temperatures.

Abstract: A semiconductor device of an aspect of the invention comprises a first internal lead provided in a lead frame, and a semiconductor chip which is mounted on the lead frame and has a plurality of first pads provided along a first side, wherein the first internal lead has a first wiring portion extending in a direction parallel to the first side, the first side is arranged to vertically overlap the first wiring portion, and the first pad is connected with the first wiring portion.

Abstract: An aspect of the semiconductor device comprising a package substrate which has a plurality of pads to which a power supply voltage is applied on an upper surface thereof, a first memory chip which is arranged on the package substrate and has a first power supply pad provided on a first side and a second power supply pad provided on a second side perpendicular to the first side, and a second memory chip which is translated in a direction along which the first and second power supply pads of the first memory chip are exposed, arranged on the first memory chip, and has the same structure as the first memory chip, wherein the first and second power supply pads are provided at diagonal corners of the first memory chip, respectively.

Abstract: A detergent for removing deposits on a mold for use in molding a thermoplastic resin, comprising limonene and ethanol is disclosed. Provided, is a detergent for removing mold deposits, said detergent being capable of easily removing deposits (the so-called mold deposits) and anticorrosive agents, releasing agents, lubricants and the like from the surface of a mold in the process of molding the thermoplastic resin. Furthermore, the detergent is preferable from the viewpoint of the work environment, and said detergent can be apply to a wide range of thermoplastic resins.

Abstract: A method for cleaning an article to be cleaned with oily deposits by using a detergent comprising 25˜80% by weight of (A) a terpene-based hydrocarbon and/or hydrocarbon-based solvent having a solubility parameter of 8.0˜9.8 and 75˜20% by weight of (B) an alcohol including one or more hydroxyl groups and having a solubility parameter of 10˜15, wherein said detergent in a state of having a water content of 10% by weight or less is coated onto the article to be cleaned and then causes the oily deposits to release from said article.

Abstract: Disclosed is a cleaning composition for use in cleaning the interior of a molding machine having residual molding resin retained therein, comprising (a) a specific graft polymer comprised of a main chain comprising an olefin polymer and having, grafted thereto, a side chain comprising a styrene polymer and (b) a thermoplastic styrene polymer, the graft polymer (a) and the thermoplastic styrene polymer (b) being present in a weight ratio of from 2/100 to 160/100. This cleaning composition exhibits an extremely excellent cleaning effect due to its high capability to scape off a residual resin on a metallic surface. By using this cleaning composition, the cleaning of the interior of a molding machine having a residual molding resin retained therein can be effectively and efficiently performed in a short period of time and at a low cost.