Patents by Inventor Mikihiko Yamada

Mikihiko Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7706400
    Abstract: A processor detects a data error in the TS packet by utilizing a value of “adaptation_field_control” and a value of “adaptation_field_length” included in the TS packet of a transport stream. A TS packet filter of the processor deletes the relevant TS packet in the transport stream if the data error in the TS packet is detected, and outputs the relevant TS packet to a PID filter if the data error in the TS packet is not detected. The PID filter detects PCR (Program Time Clock) from the TS packet. In a period of time when the PCR does not arrive at a clock reproducer, a frequency of a reference clock when the last PCR arrived is maintained, and then, when the PCR arrives at the clock reproducer, a value of STC (System Time Clock) is set and the frequency of the reference clock CK is controlled by the clock reproducer such that the value of the STC becomes equal to a value of the new PCR.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: April 27, 2010
    Assignee: Panasonic Corporation
    Inventor: Mikihiko Yamada
  • Patent number: 7680946
    Abstract: A stream data processor suitable for various applications and which performs the process of various types of stream inputs in packet data. In the stream data processor which decides individually and sequentially whether packets forming an input stream are to be processed by a predetermined process, after stream data is temporarily stored packet by packet, packet selection and data processing based on a packet identifier present in any bit position are possible.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: March 16, 2010
    Assignee: Panasonic Corporation
    Inventors: Mikihiko Yamada, Shouichi Gotoh, Satoshi Okamoto
  • Patent number: 7359441
    Abstract: In a packet data processing determination apparatus (DBA1) for respectively and sequentially determining a plurality of packet data (P) composing an inputted transport stream (TS), a packet data storage section (270) stores the packet data (P) for a predetermined time period in the order in which they came. A stored packet data identifying section (270, 260) reads identification information (PIDe) from the stored packet data (P). A target packet data determining section (400) compares the read identification information (PIDe) with predetermined process information (PIDd) to determine whether the packet data (P) is to be processed.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: April 15, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mikihiko Yamada, Shouichi Gotoh, Norihiko Mizobata
  • Publication number: 20080008100
    Abstract: A processor detects a data error in the TS packet by utilizing a value of “adaptation_field_control” and a value of “adaptation_field_length” included in the TS packet of a transport stream. A TS packet filter of the processor deletes the relevant TS packet in the transport stream if the data error in the TS packet is detected, and outputs the relevant TS packet to a PID filter if the data error in the TS packet is not detected. The PID filter detects PCR (Program Time Clock) from the TS packet. In a period of time when the PCR does not arrive at a clock reproducer, a frequency of a reference clock when the last PCR arrived is maintained, and then, when the PCR arrives at the clock reproducer, a value of STC (System Time Clock) is set and the frequency of the reference clock CK is controlled by the clock reproducer such that the value of the STC becomes equal to a value of the new PCR.
    Type: Application
    Filed: May 27, 2005
    Publication date: January 10, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Mikihiko Yamada
  • Patent number: 7280566
    Abstract: In a multi-format transport stream decoder that performs a desired process on first transport streams of different formats to generate a second transport stream, a process request information input unit (APR) is supplied with process target packet data (Pi) and process request information (ScW) indicative of process details. A stream identification information providing unit (TSRi) provides stream identification information (TSID). A packet data retaining and identifying unit (DBA) retains each pieces of first packet data (Pi), and compares the stream identification information (TSIDe) and packet data identification information (PIDe) of the first packet data (Pi) with the process request information (ScW) to determine whether the information is to be processed.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: October 9, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoshi Okamoto, Shouichi Gotoh, Mikihiko Yamada, Norihiko Mizobata
  • Patent number: 7257702
    Abstract: With a temporary operating unit being operating, a user provides a boot timing using a boot timing instructing unit. This causes a CPU to compute a boot preparation timing based on the boot timing, and store the boot timing and boot preparation timing to a boot timing memory. At this time, a timer begins a time-keeping operation. After that, the user turns off the power to the temporary operating unit. A boot preparation instructing unit determines whether or not the time being measured by the timer coincides with the boot preparation timing stored in the boot timing memory. When the time measured by the timer coincides with the boot preparation timing stored in the boot timing memory, the boot preparation instructing unit provides the CPU with a boot preparation instruction. This turns on the power to the temporary operating unit, and the CPU performs a boot preparation.
    Type: Grant
    Filed: April 16, 2004
    Date of Patent: August 14, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mikihiko Yamada, Norihiko Mizobata, Taku Arakawa
  • Publication number: 20060184780
    Abstract: With a temporary operating unit being operating, a user provides a boot timing using a boot timing instructing unit. This causes a CPU to compute a boot preparation timing based on the boot timing, and store the boot timing and boot preparation timing to a boot timing memory. At this time, a timer begins a time-keeping operation. After that, the user turns off the power to the temporary operating unit. A boot preparation instructing unit determines whether or not the time being measured by the timer coincides with the boot preparation timing stored in the boot timing memory. When the time measured by the timer coincides with the boot preparation timing stored in the boot timing memory, the boot preparation instructing unit provides the CPU with a boot preparation instruction. This turns on the power to the temporary operating unit, and the CPU performs a boot preparation.
    Type: Application
    Filed: April 16, 2004
    Publication date: August 17, 2006
    Inventors: Mikihiko Yamada, Norihiko Mizobata, Taku Arakawa
  • Publication number: 20040215803
    Abstract: A stream data processor suitable for various applications and which performs the process of various types of stream inputs in packet data. In the stream data processor which decides individually and sequentially whether packets forming an input stream are to be processed by a predetermined process, after stream data is temporarily stored packet by packet, packet selection and data processing based on a packet identifier present in any bit position are possible.
    Type: Application
    Filed: May 12, 2004
    Publication date: October 28, 2004
    Inventors: Mikihiko Yamada, Shouichi Gotoh, Satoshi Okamoto
  • Patent number: 6806818
    Abstract: A stream conversion apparatus 10 receives an MPEG2 transport stream as an input stream 21. To each packet contained in this stream, a time stamp assignment section 11 assigns the input time of that packet as a time stamp. A packet reduction section 12 deletes NULL packets which appear in the stream with a predetermined repetition pattern. Based on a proportions of the NULL packet in the stream, a time stamp replacement section 13 replaces the time stamp assigned to the packets which have not been deleted by the packet reduction section 12. The packets which have under gone the selective time stamp replacement are temporarily stored in the buffer 14, and outputted by the packet reading section 15 and the output section 16, such that each packet is outputted at a time indicated by the time stamp assigned to that packet.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: October 19, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kouichi Kita, Shouichi Gotoh, Mikihiko Yamada
  • Patent number: 6779724
    Abstract: There have been a problem that if the capacity of a receiving buffer is small, data cannot be reliably received and another problem that the rate of detection of transmission errors caused by influence of noise is low. The IC card connector comprises a receiving buffer status flag (305) set up when a receiving buffer (304) cannot hold any more data, an overrun inspecting section (306) for detecting reception of another data while the receiving buffer status flag (305) is set up, and a resending request signal generating section (102) for requesting an IC card to resend the received data if the overrun inspecting section (306) detects overrun. If a receiving buffer (304) receives another data though the receiving buffer (304) cannot hold any more data, the IC card is requested to resend the data, and the same data is received again.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: August 24, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Mikihiko Yamada
  • Publication number: 20040081148
    Abstract: In a packet data processing determination apparatus (DBA1) for respectively and sequentially determining a plurality of packet data (P) composing an inputted transport stream (TS), a packet data storage section (270) stores the packet data (P) for a predetermined time period in the order in which they came. A stored packet data identifying section (270, 260) reads identification information (PIDe) from the stored packet data (P). A target packet data determining section (400) compares the read identification information (PIDe) with predetermined process information (PIDd) to determine the packet data (P) is to be processed.
    Type: Application
    Filed: August 7, 2003
    Publication date: April 29, 2004
    Inventors: Mikihiko Yamada, Shouichi Gotoh, Norihiko Mizobata
  • Publication number: 20040076194
    Abstract: In a multi-format transport stream decoder that performs a desired process on first transport streams of different formats to generate a second transport stream, a process request information input unit (APR) is supplied with process target packet data (Pi) and process request information (ScW) indicative of process details. A stream identification information providing unit (TSRi) provides stream identification information (TSID). A packet data retaining and identifying unit (DBA) retains each pieces of first packet data (Pi), and compares the stream identification information (TSIDe) and packet data identification information (PIDe) of the first packet data (Pi) with the process request information (ScW) to determine whether the information is to be processed.
    Type: Application
    Filed: August 21, 2003
    Publication date: April 22, 2004
    Inventors: Satoshi Okamoto, Shouichi Gotoh, Mikihiko Yamada, Norihiko Mizobata
  • Publication number: 20040004562
    Abstract: A stream conversion apparatus 10 receives an MPEG2 transport stream as an input stream 21. To each packet contained in this stream, a time stamp assignment section 11 assigns the input time of that packet as a time stamp. A packet reduction section 12 deletes NULL packets which appear in the stream with a predetermined repetition pattern. Based on a proportions of the NULL packet in the stream, a time stamp replacement section 13 replaces the time stamp assigned to the packets which have not been deleted by the packet reduction section 12. The packets which have under gone the selective time stamp replacement are temporarily stored in the buffer 14, and outputted by the packet reading section 15 and the output section 16, such that each packet is outputted at a time indicated by the time stamp assigned to that packet.
    Type: Application
    Filed: July 3, 2003
    Publication date: January 8, 2004
    Inventors: Kouichi Kita, Shouichi Gotoh, Mikihiko Yamada
  • Patent number: 6288750
    Abstract: In an effective display area, an additional information recognizing part 203 recognizes a standard of a broadcast wave, refers to a ROM 212 and selects a target value, and provides an internal clock of a video data reading part 205 and an internal clock of an OSD data reading part 206 with the target value. At a retrace interval, on the other hand, the additional information recognizing part 203 notifies an additional information synthetic position deciding part 210 of the standard of the broadcast wave. The additional information synthetic position deciding part 210 selects from a ROM 211 a target value for reading the additional information applicable to the notified standard, and outputs the target value to an additional information reading parts 207. When the standard of the broadcast wave is changed, target values corresponding to the changes are responsively selected from the ROM 212 and the ROM 211.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: September 11, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mikihiko Yamada, Hirotoshi Uehara
  • Patent number: RE38954
    Abstract: In an effective display area, an additional information recognizing part 203 recognizes a standard of a broadcast wave, refers to a ROM 212 and selects a target value, and provides an internal clock of a video data reading part 205 and an internal clock of an OSD data reading part 206 with the target value. At a retrace interval, on the other hand, the additional information recognizing part 203 notifies an additional information synthetic position deciding part 210 of the standard of the broadcast wave. The additional information synthetic position deciding part 210 selects from a ROM 211 a target value for reading the additional information applicable to the notified standard, and outputs the target value to an additional information reading parts 207. When the standard of the broadcast wave is changed, target values corresponding to the changes are responsively selected from the ROM 212 and the ROM 211.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: January 31, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mikihiko Yamada, Hirotoshi Uehara
  • Patent number: RE40606
    Abstract: In an effective display area, an additional information recognizing part 203 recognizes a standard of a broadcast wave, refers to a ROM 212 and selects a target value, and provides an internal clock of a video data reading part 205 and an internal clock of an OSD data reading part 206 with the target value. At a retrace internal, on the other hand, the additional information recognizing part 203 notifies an additional information synthetic position deciding part 210 of the standard of the broadcast wave. The additional information synthetic position deciding part 210 selects from a ROM 211 a target value for reading the additional information applicable to the notified standard, and outputs the target value to an additional information reading parts 207. When the standard of the broadcast wave is changed, target values corresponding to the changes are responsively selected from the ROM 212 and the ROM 211.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: December 16, 2008
    Assignee: Panasonic Corporation
    Inventors: Mikihiko Yamada, Hirotoshi Uehara