Abstract: The present invention relates to a technique, in the inspection of a defect of a semiconductor memory or the like, in which chip comparison is separated from repetitive pattern comparison in a region of a wafer to be inspected whereby both the comparisons are rendered possible to perform in parallel in one and the same scanning.

Abstract: A pattern defect inspection apparatus detects presence or absence of a defect in a pattern formed on a semiconductor wafer by scanning the pattern normally to the surface thereof by a coherent light beam of a predetermined spot size, detecting reflected diffraction lights generated thereby and processing the detected lights. It comprises an abnormal direction signal detector including photo-detectors having wide light receiving areas arranged in a plurality of spatial areas which the reflected diffraction lights from a normal pattern do not normally reach, a normal pattern detector including photo-detectors having large light receiving areas arranged in a plurality of spatial areas which the reflected diffraction lights from the normal pattern reach, and a defect discriminator for determining if the abnormal direction signals are due to a true defect or not in accordance with the signals from the abnormal direction signal detector and the normal pattern detector.