Abstract: A semiconductor device includes a logic circuit, a memory circuit having a plurality of first static memory cells formed by a transistor on the semiconductor substrate, a monitor circuit having a second static memory cell formed by a transistor on the semiconductor substrate, the monitor circuit being configured to apply stress to the second static memory cell during a period in which the semiconductor device operates so that a state of the second static memory cell can be notified, and a bus coupled with the logic circuit, the memory circuit and the monitor circuit, wherein a size of the transistor of one cell of the first static memory cells is substantively the same as that of the transistor of the second static memory cell.

Abstract: A semiconductor device includes a logic circuit, a memory circuit having a plurality of first static memory cells formed by a transistor on the semiconductor substrate, a monitor circuit having a second static memory cell formed by a transistor on the semiconductor substrate, the monitor circuit being configured to apply stress to the second static memory cell during a period in which the semiconductor device operates so that a state of the second static memory cell can be notified, and a bus coupled with the logic circuit, the memory circuit and the monitor circuit, wherein a size of the transistor of one cell of the first static memory cells is substantively the same as that of the transistor of the second static memory cell.

Abstract: A semiconductor device suitable for predicting failures is provided. A semiconductor device including a logic circuit and a static memory having a plurality of first static memory cells formed on a semiconductor substrate, further includes a monitor memory circuit having a second static memory cell formed on the semiconductor substrate, and a monitor circuit MON applying stress to the second static memory cell during a period in which the semiconductor device operates so that a state of the second static memory cell can be notified.

Abstract: A semiconductor device suitable for predicting failures is provided. A semiconductor device including a logic circuit and a static memory having a plurality of first static memory cells formed on a semiconductor substrate, further includes a monitor memory circuit having a second static memory cell formed on the semiconductor substrate, and a monitor circuit MON applying stress to the second static memory cell during a period in which the semiconductor device operates so that a state of the second static memory cell can be notified.

Abstract: In order to obtain a solenoid valve device installed in a gas tank that is small in size and easy to attach to a gas tank, a valve body (8) including a flow passage (a) formed therein to communicate the inside and the outside of a gas tank (1) is inserted to the inside from the outside through a mouth hole (2) of the gas tank (1) and attached to the mouth hole (2). A valve seat (46) is provided in the flow passage (a), and a movable valve element (40) attached to or detached from the valve seat (46) is provided in the valve body (8). A solenoid unit (48) includes a movable core (50) engaged with the valve element (40) and a fixed core (64) facing the movable core (50) to attract the movable core (50) by the energization of a coil (74) and distract the movable core (50) by the non-energization of the coil (74). The solenoid unit (48) is arranged inside a storage hole (16) formed at an end part of the valve body (8) inside the gas tank (1).

Abstract: In order to obtain a solenoid valve device installed in a gas tank that is small in size and easy to attach to a gas tank, a valve body (8) including a flow passage (a) formed therein to communicate the inside and the outside of a gas tank (1) is inserted to the inside from the outside through a mouth hole (2) of the gas tank (1) and attached to the mouth hole (2). A valve seat (46) is provided in the flow passage (a), and a movable valve element (40) attached to or detached from the valve seat (46) is provided in the valve body (8). A solenoid unit (48) includes a movable core (50) engaged with the valve element (40) and a fixed core (64) facing the movable core (50) to attract the movable core (50) by the energization of a coil (74) and distract the movable core (50) by the non-energization of the coil (74). The solenoid unit (48) is arranged inside a storage hole (16) formed at an end part of the valve body (8) inside the gas tank (1).

Abstract: A semiconductor test device capable of solving a problem of a conventional one in that in the resistance measurement of a semiconductor integrated circuit it was difficult for the measurement error due to contact resistance or wiring resistance to be limited within a desired amount. The present semiconductor test device includes, in a semiconductor integrated circuit having a first semiconductor switch functioning as a pullup resistor and a second semiconductor switch functioning as a pulldown resistor, a measuring circuit for bringing the first and second semiconductor switches into conduction at the same time in response to a signal fed from a control circuit, a voltage measuring circuit for measuring the voltage at a connecting point between the two semiconductor switches, and a current measuring circuit for measuring a through current flowing through the two semiconductor switches.

Abstract: A mixer blade assembly is provided for medium and high viscosity liquid which does not cause the generation of an insufficiently mixed region of a doughnut-shaped configuration within the liquid to be mixed and therefore has excellent mixing performance. The mixer blade assembly for medium and high viscosity liquid includes a rotary shaft including at least two support posts spaced apart from each other; a plurality of plate-shaped inclined blades secured on each of the support posts and spaced apart from each other into multiple stages, the leading edge of each of the blades being displaced rearwardly or forwardly as viewed from the axis of blade rotation from the upper stage to the lower stage; and a bottom impeller secured on the support posts and being located in proximity with the bottom surface of the mixing vessel.

Abstract: A bare chip (1) is rectangular, and has a front surface (1a) on the center of which semiconductor elements are integrated and a back surface. Notches (2) are formed on a side of the bare chip (1) according to the kind of the semiconductor elements integrated on the bare chip (1). The notches (2) are oblong and extend through the bare chip (1) from the front surface (1a) to the back surface. For example, assuming that the notch (2) represents "1" and a portion without the notch (2) represents "0", one-bit information is obtained according to the presence or absence of the notch (2). When detection of several portions is made, binary information according to a detection result, i.e., information regarding the type of the bare chip (1), is obtained. For detection of the presence or absence of the notch (2), the bare chip (1) is irradiated with light, and then whether the light goes through the notch (2) or is intercepted by the bare chip (1) is detected.

Abstract: A semiconductor integrated device including a first circuit block, a second circuit block, a first supply interconnection connected to the first circuit block to supply power thereto, a second supply interconnection connecting the first supply interconnection to the second circuit block, and a switch inserted across the first and second supply interconnections. The switch has a structure equivalent to a plurality of switching elements disposed in parallel on a substrate. The switch is opened by a break command output from the first circuit block so that the second supply interconnection is disconnected from the first supply interconnection, thereby preventing a standby current from flowing to the second circuit block when it is unused. This can solve a problem of a conventional semiconductor integrated device in that the standby current flowing to the second circuit block wastes power even if the second block is not used.

Abstract: An agitating vane in which a plate-like vane is disposed at an extreme end of a rotary shaft to agitate liquid has a feature that auxiliary vanes for covering a part of vane with a clearance being left are disposed in front of the surface of the vane in its rotational direction. Accordingly, a phenomenon of peeling-off caused by the eddy flow generated at the rear surface of the vane is eliminated by liquid flowing at a high speed at a clearance between the vane and the auxiliary vanes, a circulation flow of regulated flow state is attained and agitating efficiency is improved.