Patents by Inventor Mikio Hondou
Mikio Hondou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8655935Abstract: A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information and a floating point multiply-adder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register.Type: GrantFiled: March 13, 2008Date of Patent: February 18, 2014Assignee: Fujitsu LimitedInventors: Mikio Hondou, Ryuji Kan, Toshio Yoshida
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Patent number: 8583872Abstract: A cache memory having a sector function, operating in accordance with a set associative system, and performing a cache operation to replace data in a cache block in the cache way corresponding to a replacement cache way determined upon an occurrence of a cache miss comprises: storing sector ID information in association with each of the cache ways in the cache block specified by a memory access request; determining, upon the occurrence of the cache miss, replacement way candidates, in accordance with sector ID information attached to the memory access request and the stored sector ID information; selecting and outputting a replacement way from the replacement way candidates; and updating the stored sector ID information in association with each of the cache ways in the cache block specified by the memory access request, to the sector ID information attached to the memory access request.Type: GrantFiled: August 19, 2008Date of Patent: November 12, 2013Assignee: Fujitsu LimitedInventors: Shuji Yamamura, Mikio Hondou, Iwao Yamazaki, Toshio Yoshida
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Patent number: 8560784Abstract: A priority control register 104 dynamically controls the internal transition state based on the issuability state of a memory request obtained in the memory request issuability signal generation unit 106 and retaining state of the memory request in the REQ_BUF 102 obtained by each of determination circuits 105 #2 through #5. Thus, the jump control of the priorities corresponding to the access regulation of the DRAM module 109 can be realized.Type: GrantFiled: September 21, 2011Date of Patent: October 15, 2013Assignee: Fujitsu LimitedInventors: Noriyuki Takahashi, Mikio Hondou
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Patent number: 8533248Abstract: A processing unit computes a trigonometric function, for decrease the number of instructions and improve throughput. In a floating point multiply-add circuit, an OR circuit, a selector and an EOR circuit are disposed, and an expansion point and expansion function of the Taylor series expansion of the trigonometric function are computed using a first trigonometric function operation auxiliary instruction for defining the operation of rd=(rs1*rs1)|(rs2 [0]<<63) and a second trigonometric function operation auxiliary instruction for defining the operation of rd=((rs2 [0])? 1.0: rs1)^(rs2 [1]<<63), or a third trigonometric function operation auxiliary instruction for defining the operation of rd=(rs1*rs1)|((˜rs2 [0]<<63) and a fourth trigonometric function operation auxiliary instruction for defining the operation of rd=((rs2 [0])? rs1: 1.0)^((rs2 [1]^rs2 [0])<<63)).Type: GrantFiled: June 29, 2010Date of Patent: September 10, 2013Assignee: Fujitsu LimitedInventor: Mikio Hondou
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Patent number: 8281112Abstract: A processing unit has an extended register to which instruction extension information indicating an extension of an instruction can be set. An operation unit that, when instruction extension information is set to the extended register, executes a subsequent instruction following a first instruction for writing the instruction extension information into the extended register, extends the subsequent instruction based on the instruction extension information.Type: GrantFiled: December 18, 2008Date of Patent: October 2, 2012Assignee: Fujitsu LimitedInventors: Toshio Yoshida, Mikio Hondou
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Publication number: 20120079216Abstract: A priority control register 104 dynamically controls the internal transition state based on the issuability state of a memory request obtained in the memory request issuability signal generation unit 106 and retaining state of the memory request in the REQ_BUF 102 obtained by each of determination circuits 105 #2 through #5. Thus, the jump control of the priorities corresponding to the access regulation of the DRAM module 109 can be realized.Type: ApplicationFiled: September 21, 2011Publication date: March 29, 2012Applicant: FUJITSU LIMITEDInventors: Noriyuki TAKAHASHI, Mikio Hondou
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Patent number: 8074029Abstract: A processor equipped with a pre-fetch function comprises: first layer cache memory having a first line size; second layer cache memory that is on the under layer of the first layer cache memory and that has a second line size different from the first line size; and a pre-fetch control unit for issuing a pre-fetch request from the first layer cache memory to the second layer cache memory so as to pre-fetch a block equivalent to the first line size for each second line size.Type: GrantFiled: August 28, 2008Date of Patent: December 6, 2011Assignee: Fujitsu LimitedInventor: Mikio Hondou
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Publication number: 20110010503Abstract: A cache memory for operating in accordance with a multi-way set associative system, the cache memory includes an identification information storage for storing an identification information for identifying a requesting element of a memory access request corresponding to a cache block specified by a received memory access request, a replacement cache block candidate determinator for determining, upon an occurrence of a cache miss corresponding to the memory access request, a candidate of the cache block for replacing, on the basis of the identification information attached to the memory access request and the identification information stored in the identification information storage corresponding to the cache block specified by the memory access request, and a replacement cache block selector for selecting a replacement cache block from the candidate.Type: ApplicationFiled: June 17, 2010Publication date: January 13, 2011Inventors: Shuji YAMAMURA, Mikio HONDOU
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Publication number: 20100332573Abstract: A processing unit computes a trigonometric function, for decrease the number of instructions and improve throughput. In a floating point multiply-add circuit, an OR circuit, a selector and an EOR circuit are disposed, and an expansion point and expansion function of the Taylor series expansion of the trigonometric function are computed using a first trigonometric function operation auxiliary instruction for defining the operation of rd=(rs1*rs1)|(rs2 [0]<<63) and a second trigonometric function operation auxiliary instruction for defining the operation of rd=((rs2 [0])? 1.0: rs1)?(rs2 [1]<<63), or a third trigonometric function operation auxiliary instruction for defining the operation of rd=(rs1*rs1)|((˜rs2 [0]<<63) and a fourth trigonometric function operation auxiliary instruction for defining the operation of rd=((rs2 [0])? rs1: 1.0)?((rs2 [1]?rs2 [0])<<63)).Type: ApplicationFiled: June 29, 2010Publication date: December 30, 2010Applicant: FUJITSU LIMITEDInventor: Mikio Hondou
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Patent number: 7827393Abstract: A branch prediction apparatus reads out a branch history table 15 by an index calculated by the output of a branch history register 14 containing a plurality of the latest branch result of a branch instruction. The branch prediction apparatus comprises frequency detection units 18-20 for detecting the appearance frequency of a branch instruction with a different address and data width modification units 16 and 21 for modifying the number of valid bits of the branch history register, based on the detected appearance frequency. Even a program in which a branch result strongly depends on the latest branch history or even a program having a plenty of branch instructions can maintain high prediction accuracy with a small capacity of the branch history table.Type: GrantFiled: September 6, 2006Date of Patent: November 2, 2010Assignee: Fujitsu LimitedInventor: Mikio Hondou
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Publication number: 20090172367Abstract: A processing unit has an extended register to which instruction extension information indicating an extension of an instruction can be set. An operation unit that, when instruction extension information is set to the extended register, executes a subsequent instruction following a first instruction for writing the instruction extension information into the extended register, extends the subsequent instruction based on the instruction extension information.Type: ApplicationFiled: December 18, 2008Publication date: July 2, 2009Applicant: Fujitsu LimitedInventors: Toshio Yoshida, Mikio Hondou
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Publication number: 20090172289Abstract: A cache memory having a sector function, operating in accordance with a set associative system, and performing a cache operation to replace data in a cache block in the cache way corresponding to a replacement cache way determined upon an occurrence of a cache miss comprises: storing sector ID information in association with each of the cache ways in the cache block specified by a memory access request; determining, upon the occurrence of the cache miss, replacement way candidates, in accordance with sector ID information attached to the memory access request and the stored sector ID information; selecting and outputting a replacement way from the replacement way candidates; and updating the stored sector ID information in association with each of the cache ways in the cache block specified by the memory access request, to the sector ID information attached to the memory access request.Type: ApplicationFiled: August 19, 2008Publication date: July 2, 2009Applicant: FUJITSU LIMITEDInventors: Shuji YAMAMURA, Mikio HONDOU, Iwao YAMAZAKI, Toshio YOSHIDA
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Publication number: 20090037663Abstract: A processor equipped with a pre-fetch function comprises: first layer cache memory having a first line size; second layer cache memory that is on the under layer of the first layer cache memory and that has a second line size different from the first line size; and a pre-fetch control unit for issuing a pre-fetch request from the first layer cache memory to the second layer cache memory so as to pre-fetch a block equivalent to the first line size for each second line size.Type: ApplicationFiled: August 28, 2008Publication date: February 5, 2009Applicant: FUJITSU LIMITEDInventor: Mikio HONDOU
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Publication number: 20080228846Abstract: A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information and a floating point multiply-adder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register.Type: ApplicationFiled: March 13, 2008Publication date: September 18, 2008Applicant: FUJITSU LIMITEDInventors: Mikio HONDOU, Ryuji Kan, Toshio Yoshida
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Publication number: 20070005945Abstract: A branch prediction apparatus reads out a branch history table 15 by an index calculated by the output of a branch history register 14 containing a plurality of the latest branch result of a branch instruction. The branch prediction apparatus comprises frequency detection units 18-20 for detecting the appearance frequency of a branch instruction with a different address and data width modification units 16 and 21 for modifying the number of valid bits of the branch history register, based on the detected appearance frequency. Even a program in which a branch result strongly depends on the latest branch history or even a program having a plenty of branch instructions can maintain high prediction accuracy with a small capacity of the branch history table.Type: ApplicationFiled: September 6, 2006Publication date: January 4, 2007Applicant: FUJITSU LIMITEDInventor: Mikio Hondou
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Patent number: 6760836Abstract: An instruction issuing device comprises a plurality of issue controlling circuits which run in parallel, and perform a control for preferentially issuing an instruction to a particular arithmetic unit. An optimum issue controlling circuit is selected according to the empty quantity of instruction slots for each arithmetic unit or a result of learning of the number of previously issued instructions, and an issue destination is determined based on the direction of the selected circuit.Type: GrantFiled: March 5, 2001Date of Patent: July 6, 2004Assignee: Fujitsu LimitedInventor: Mikio Hondou
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Publication number: 20020019927Abstract: An instruction issuing device comprises a plurality of issue controlling circuits which run in parallel, and perform a control for preferentially issuing an instruction to a particular arithmetic unit. An optimum issue controlling circuit is selected according to the empty quantity of instruction slots for each arithmetic unit or a result of learning of the number of previously issued instructions, and an issue destination is determined based on the direction of the selected circuit.Type: ApplicationFiled: March 5, 2001Publication date: February 14, 2002Inventor: Mikio Hondou