Patents by Inventor Mikio Kamiya

Mikio Kamiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6587916
    Abstract: A microcomputer comprises: a flash memory for storing rewriting control F/W and user S/F; a command register for specifying content of rewriting control; a address register to be subjected to rewriting-control; a data register for specifying data to be written; a power-supply pump circuit in the flash memory; and a control signal register for specifying/outputting a control signal to a memory decoder. A CPU of the microcomputer is capable of accessing these four registers to perform writing or reading. A given bit of the control signal register corresponds to a given control signal. A value written to the register becomes a control signal that will be directly supplied to both of the power supply circuit and the memory decoder, in the flash memory, to control them. By rewriting a set value of this control signal register using the rewriting control F/W according to a specified sequence, processing such as “erase” and “program” of the flash memory is performed.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: July 1, 2003
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Semiconductor System Corporation, Mitsubishi Electric Engineering Company Limited
    Inventors: Katsunobu Hongo, Tsutomu Tanaka, Toshihiro Sezaki, Hiroyuki Kimura, Mikio Kamiya, Yasuhiro Ami, Kunio Tani, Tomohisa Iba
  • Patent number: 6459640
    Abstract: A nonvolatile semiconductor memory includes a memory block composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a nonvolatile transistor; a memory decoder necessary for erasing/writing/reading data of the nonvolatile transistor in the memory array; a charge pump necessary for erasing/writing/reading the data of the nonvolatile transistor in the memory array; a register having each of a plurality of control signals for controlling the memory decoder and the charge pump allocated to register 1 bit; and an updating device for updating a content of the register by a data processor coupled to the register. By using this updating device to update the content of the register, the memory decoder and the charge pump are controlled, the data of the memory block is erased, and data is written in/read from the nonvolatile transistor.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: October 1, 2002
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Comp. Limited, Mitsubishi Electric Semiconductor System Corp.
    Inventors: Kunio Tani, Tomohisa Iba, Tetsu Tashiro, Katsunobu Hongo, Tsutomu Tanaka, Mikio Kamiya, Toshihiro Sezaki, Hiroyuki Kimura
  • Publication number: 20020129195
    Abstract: A microcomputer comprises: a flash memory for storing rewriting control F/W and user S/F; a command register for specifying content of rewriting control; a address register to be subjected to rewriting-control; a data register for specifying data to be written; a power-supply pump circuit in the flash memory; and a control signal register for specifying/outputting a control signal to a memory decoder. A CPU of the microcomputer is capable of accessing these four registers to perform writing or reading. A given bit of the control signal register corresponds to a given control signal. A value written to the register becomes a control signal that will be directly supplied to both of the power supply circuit and the memory decoder, in the flash memory, to control them. By rewriting a set value of this control signal register using the rewriting control F/W according to a specified sequence, processing such as “erase” and “program” of the flash memory is performed.
    Type: Application
    Filed: September 7, 2001
    Publication date: September 12, 2002
    Inventors: Katsunobu Hongo, Tsutomu Tanaka, Toshihiro Sezaki, Hiroyuki Kimura, Mikio Kamiya, Yasuhiro Ami, Kunio Tani, Tomohisa Iba
  • Publication number: 20020101764
    Abstract: There is provided a nonvolatile semiconductor memory comprising: a memory bock composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a nonvolatile transistor; a memory decoder necessary for erasing/writing/reading data of the nonvolatile transistor in the memory array; a charge pump necessary for erasing/writing/reading the data of the nonvolatile transistor in the memory array; a register having each of a plurality of control signals for controlling the memory decoder and the charge pump allocated to register 1 bit; and means for updating a content of the register by a data processor coupled to the register. By using this updating means to update the content of the register, the memory decoder and the charge pump are controlled, the data of the memory block is erased, and data is written in/read from the nonvolatile transistor.
    Type: Application
    Filed: August 17, 2001
    Publication date: August 1, 2002
    Inventors: Kunio Tani, Tomohisa Iba, Tetsu Tashiro, Katsunobu Hongo, Tsutomu Tanaka, Mikio Kamiya, Toshihiro Sezaki, Hiroyuki Kimura