Abstract: A detection apparatus having means for evaluating generation and disappearance of a carrier is provided. A detection apparatus detects, on the basis of high-order harmonics, an electric field distribution or a carrier distribution between electrodes arranged on an object to be observed.

Abstract: An optical device having: an optical fiber body; a ferrule which surrounds the above described optical fiber body and to which a recess that crosses a coreless fiber within the above described optical fiber has been provided; and an optical element which is provided within the recess in said ferrule, is provided with a protective member for protecting the above described recess, and the protective member has a restriction means for physically restricting the rotation of the optical device around the optical axis.

Abstract: An optical device having: an optical fiber body; a ferrule which surrounds the above described optical fiber body and to which a recess that crosses a coreless fiber within the above described optical fiber has been provided; and an optical element which is provided within the recess in said ferrule, is provided with a protective member for protecting the above described recess, and the protective member has a restriction means for physically restricting the rotation of the optical device around the optical axis.

Abstract: On one principal plane of a silicon substrate 1, a silicon oxide film 2 having an opening 2a is formed, and a silicon nitride film 3 having an opening 3b overlapping the opening 2a and a recessed marker 3b is stacked on the silicon oxide film 2. Next, the substrate 1 is etched through the openings 2a, 3a to provide an alignment groove 1a for an optical waveguide, and an electrode pattern 5 is formed. Light of which wavelength transmits through the substrate 1 and the silicon oxide film 2 is radiated from the other principal plane of the substrate 1, and the optical element is assembled with the marker 3b serving as the reference while the marker 3b and the optical element are monitored.

Abstract: A light emitting unit including a light emitting device of a light emitting module for optical communication is constituted by a laser diode for emitting communication light, a sub-mount having a good thermal conductivity and holding the laser diode on its upper surface, a heat sink for removing the heat generated by the laser diode, a photodiode for monitoring a light output from the laser diode, a laser driver IC which is thermally isolated from the laser diode, has an electric contact placed near the electric contact of the laser diode and connected thereto by wire bonding, and drives the laser diode, and a metal package for holding the heat sink, the photodiode, and the laser driver IC. A light emitting module for optical communication uses the light emitting unit.

Abstract: A photodetector unit for a photodetector module for optical communication includes a photodetector circuit unit constituted by a ceramic board on which a photodiode for converting input light into an electrical signal and a preamplifier IC connected to the photodiode by bump bonding are mounted, and which has a photodetector circuit connected to the preamplifier IC by bump bonding, and a main amplification circuit unit constituted by a ceramic board on which a main amplification IC is mounted, and which has a main amplification circuit connected to the main amplification IC by bump bonding. The ceramic boards of the photodetector circuit unit and the main amplification circuit unit are mechanically and electrically connected to each other such that a mount surface of the preamplifier IC becomes perpendicular to a mount surface of the main amplification IC.

Abstract: This receptacle comprises a case made of resin, holding a rigid sleeve by being in contact with the outer wall of the rigid sleeve, having a through hole communicating with the through hole of the rigid sleeve at one end thereof.

Abstract: The plurality of functioning circuits are formed in a plurality of P-type well regions formed on a remaining part of said low concentration N-type layer, by isolating from each other. According to the present invention, the photoelectric current from the PIN photodiode can be processed in the functioning circuits formed in the P-type well regions by isolating from each other, so that the interference between the functioning circuits can be prevented and also the shift of the current flowing in each functioning circuit due to the impossibility of the high concentration N-type semiconductor layer to be grounded can be prevented. Therefore, the malfunction of the integrated PIN photodiode sensor can be prevented, and the PIN photodiode sensor can operate with high speed because the distributed resistance between the functioning circuits is decreased.

Abstract: This invention relates to a monolithic IC having a PIN photodiode and an n-p-n bipolar transistor formed on a single semiconductor (silicon) substrate. In fabricating such IC, it is important to electrically isolate the photodiode and the bipolar transistor. In addition it is necessary to make the surface of the substrate flat. According to this invention, the inter-device isolation between the above-described two devices is attained by forming two epitaxial layers on the silicon substrate, forming trenches in the layers, and burying silicon dioxide in the trenches. In the monolithic IC according to this invention wiring capacity is small, and high-speed performance becomes possible. A p-type buried-layer is formed below the bipolar transistor to thereby prevent punch through between the bipolar transistor and other devices. Also this invention provides the process for fabricating a planar type bipolar transistor suitable to fabricate the monolithic IC and also provides a PIN photodiode of a new structure.

Abstract: An integrated circuit includes an operational amplifier having inverting and noninverting input terminals, a first logarithmic amplifier having inverting and noninverting input terminals, and a second logarithmic amplifier having inverting and noninverting input terminals. The output of the first logarithmic amplifier is connected to the noninverting input terminal of the second logarithmic amplifier, and the output of the second logarithmic amplifier is connected to the inverting input terminal of the operational amplifier.

Abstract: A semiconductor photodiode device comprises a substrate with top and bottom opposite surfaces, having an upper portion of a first conductivity type adjacent the top surface and a lower portion of a second conductivity type adjacent the bottom surface, an anode region of the second conductivity type and a cathode region of the first conductivity type radially spaced from the anode region and disposed in the top surface of the substrate, and an isolation region of the second conductivity type disposed in the upper portion of the substrate radially spaced from the surrounding the cathode and anode regions. The isolation region extends to the lower portion of the substrate. A buried region of the first conductivity type underlies a portion of the top surface of the substrate enclosed by the cathode region and spaced from the anode, cathode and isolation regions such that the buried region is in contact with the upper and lower portions of the substrate.

Abstract: An image sensor particularly suitable for use in an autofocus camera includes a light measuring means, a capacitance element for accumulating picture element information which is photoelectrically converted by the light measuring means, a source follower circuit that outputs as picture element information the voltage across the capacitance element with low output impedance, a switching element for reading out the picture element information from the source follower to a video line, and a load element for outputting the output voltage of the source follower to a monitor line. The output voltage from the source follower to the monitor line is compared with a reference voltage which has been preset to a desired output voltage level.

Abstract: A solid state image sensor in which the charge accumulation period of each picture element can be set at the same point of time. Additionally, the lenngth of the charge period can be set at will, thus providing a video signal picture in which all picture elements bear image information with the same time reference. Sensitivity of the solid state image senosr can be adjusted by setting the length of charge accumulation period. In the solid state image sensor, photodiodes are disposed as picture elements, and video signal is output in accordance with a charge which is light-generated within respective photodiodes. A series circuit of a switch and a capacitance element is connected in parallel with the photodiode. The switch is closed for at least the charge accumulation period during which charge is light-generated within the photodiode, and the video signal is obtained in accordance with level of charging of said capacitance element.

Abstract: A programmable logic array includes a plurality of semiconductor memory elements, such as FAMOSs, arranged in the form of an array and a sense circuit for receiving data out from the memory elements during read out mode. The present programmable logic array is so structured that the sense circuit is rendered operative for a predetermined time period every time when an input signal to the array changes its state thereby allowing to minimize the power consumption.

Abstract: A semiconductor memory device is provided with a memory region including SAMOS type memory transistors and a non-memory or peripheral region including MOS transistors which are interconnected to form logic circuits such as decoders for controlling the operation of each of said memory transistors. Each of the transistors includes a pair of first and second doped polysilicon layers and an interlayer insulating film provided as sandwiched between the pair of first and second doped polysilicon layers. In the memory region, the first and second doped polysilicon layers define floating and control gate electrodes, respectively; whereas, in the non-memory region, the first and second doped polysilicon layers are electrically interconnected by a through-the-layer electrode formed through the interlayer insulating film.

Abstract: An input buffer circuit comprised of MOS transistors includes an input terminal for receiving a tri-state input signal capable of taking any one of three potential levels, such as V.sub.pp, V.sub.cc and V.sub.ss. The input buffer circuit also includes a first detecting circuit having a first threshold level located between V.sub.pp and V.sub.cc and a second detecting circuit having a second threshold level located between V.sub.cc and V.sub.ss. Also provided is a third detecting circuit connected to the first and second detecting circuits to determine the level of the input signal applied to the input terminal.

Abstract: An erasable field programmable logic array including a matrix of reprogrammable memory elements which may be selectively programmed to store a desired logic function therein is provided. Since use is made of reprogrammable memory elements, the stored logic function may be erased and another logic function may be programmed into the programmable logic array.

Abstract: An erasable field programmable logic array including a matrix of reprogrammable memory elements which may be selectively programmed to store a desired logic function therein is provided. Since use is made of reprogrammable memory elements, the stored logic function may be erased and another logic function may be programmed into the programmable logic array.

Abstract: A memory cell formed of two serially connected MOS transistors one of which has a floating gate is connected to a series combination of a Y address MOS transistor, a readout selection MOS transistor and an MOS transistor disposed in an output buffer circuit across two DC sources. A writing selection MOS transistor is connected across the series combination of the last-mentioned two transistors. The Y address MOS transistor, the readout selection MOS transistor, the output buffer MOS transistor and the writing selection MOS transistor are all operated in the triode region with V.sub.G -V.sub.TH >V.sub.D and at least one of these MOS transistors has a channel conductivity type different from the channel conductivity type of the memory cell MOS transistors.

Abstract: In the disclosed FAMOS semiconductor non-volatile memory a source and a drain region of the p.sup.+ type are disposed in an n semiconductor layer to form a gate region between them. The main face of the semiconductor layer is coated with a silicon dioxide film in which a polycrystalline silicon gate is buried to bridge the source and drain regions. An n.sup.+ type high doped semiconductor region is disposed in the semiconductor layer only under the silicon gate to form a pn junction with the drain region. Thus the pn junction is normal to the main face of the semiconductor layer.