Patents by Inventor Mikio Matsui

Mikio Matsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070292989
    Abstract: A semiconductor device includes a base substrate; a first fixing layer provided on the base substrate; a first semiconductor chip fixed on the first fixing layer; a first substrate provided above the first semiconductor chip; a plurality of first connection members isolated from the first semiconductor chip, electrically connecting to the first substrate with the base substrate; and a first encapsulating layer provided around the first connection members.
    Type: Application
    Filed: July 19, 2007
    Publication date: December 20, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shoko Omizo, Mikio Matsui
  • Patent number: 7276784
    Abstract: A semiconductor device includes a base substrate; a first fixing layer provided on the base substrate; a first semiconductor chip fixed on the first fixing layer; a first substrate provided above the first semiconductor chip; a plurality of first connection members isolated from the first semiconductor chip, electrically connecting to the first substrate with the base substrate; and a first encapsulating layer provided around the first connection members.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: October 2, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoko Omizo, Mikio Matsui
  • Publication number: 20060079020
    Abstract: A semiconductor device includes a base substrate; a first fixing layer provided on the base substrate; a first semiconductor chip fixed on the first fixing layer; a first substrate provided above the first semiconductor chip; a plurality of first connection members isolated from the first semiconductor chip, electrically connecting to the first substrate with the base substrate; and a first encapsulating layer provided around the first connection members.
    Type: Application
    Filed: October 11, 2005
    Publication date: April 13, 2006
    Inventors: Shoko Omizo, Mikio Matsui
  • Patent number: 6686222
    Abstract: In a semiconductor device manufacturing method, a semiconductor element is mounted on a substrate including first connection electrodes, first interconnections electrically connected to the first connection electrodes and a first alignment mark with the semiconductor element electrically connected to the first interconnections. Then, the substrate having the semiconductor element mounted thereon and a core substrate including second connection electrodes and second interconnections electrically connected to the second connection electrode and having adhesive layers formed on both surfaces thereof are positioned with respect to and stacked on each other based on recognition of the first alignment mark, thermo-compression bonding is performed at temperatures at which an adhesive agent of the adhesive layers is melted, without being cured, to temporarily fix the substrate having the semiconductor element mounted thereon on the core substrate by tackiness of the adhesive agent.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: February 3, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoko Omizo, Atsushi Yoshimura, Mikio Matsui, Takao Sato
  • Patent number: 6617678
    Abstract: There is disclosed a semiconductor device which comprises a first chip-mounting substrate on which at least one semiconductor chip having a plurality of terminals is mounted, and a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, a second chip-mounting substrate which is laminated on the first chip-mounting substrate and on which at least one semiconductor chip is mounted, a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, and at least one of the semiconductor chips has a center offset from a center of a whole arrangement of the relay terminals.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: September 9, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yamazaki, Mitsuyoshi Endo, Chiaki Takubo, Katsuhiko Oyama, Takashi Imoto, Mikio Matsui
  • Publication number: 20020195698
    Abstract: There is disclosed a semiconductor device which comprises a first chip-mounting substrate on which at least one semiconductor chip having a plurality of terminals is mounted, and a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, a second chip-mounting substrate which is laminated on the first chip-mounting substrate and on which at least one semiconductor chip is mounted, a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, and at least one of the semiconductor chips has a center offset from a center of a whole arrangement of the relay terminals.
    Type: Application
    Filed: May 16, 2002
    Publication date: December 26, 2002
    Inventors: Takashi Yamazaki, Mitsuyoshi Endo, Chiaki Takubo, Katsuhiko Oyama, Takashi Imoto, Mikio Matsui
  • Publication number: 20020187588
    Abstract: In a semiconductor device manufacturing method, a semiconductor element is mounted on a substrate including first connection electrodes, first interconnections electrically connected to the first connection electrodes and a first alignment mark with the semiconductor element electrically connected to the first interconnections. Then, the substrate having the semiconductor element mounted thereon and a core substrate including second connection electrodes and second interconnections electrically connected to the second connection electrode and having adhesive layers formed on both surfaces thereof are positioned with respect to and stacked on each other based on recognition of the first alignment mark, thermo-compression bonding is performed at temperatures at which an adhesive agent of the adhesive layers is melted, without being cured, to temporarily fix the substrate having the semiconductor element mounted thereon on the core substrate by tackiness of the adhesive agent.
    Type: Application
    Filed: May 17, 2002
    Publication date: December 12, 2002
    Inventors: Shoko Omizo, Atsushi Yoshimura, Mikio Matsui, Takao Sato
  • Patent number: 5998243
    Abstract: In a method for manufacturing a flip-chip bonded semiconductor device is used an apparatus for resin-encapsulating, the apparatus which comprises a molding die consisting of a plurality of mold bodies, device for decompressing cavities of the molding die, device for heating the molding die, and device for injecting a liquid resin under pressure into the cavities, to form a resin-encapsulating layer by transfer molding. A bonded body having a semiconductor chip connected to a wiring substrate through its bumps is placed in the cavities of the molding die, the cavities are heated and decompressed, then the liquid resin is injected under pressure into the cavities through a gate to form a resin-encapsulating layer. Thus, the molding resin can be filled uniformly into the gap between the semiconductor chip and the wiring substrate in a short time to produce a flip-chip bonded semiconductor device having good performances.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: December 7, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Teikou Odashima, Mikio Matsui, Yoshiaki Sugizaki, Takahito Nakazawa
  • Patent number: 5528329
    Abstract: A photographic film processing apparatus having a processing unit placed in a water tank and provided with a plurality of processing chambers each having a comparatively small volume, and capable of uniformly, stably, continuously and quickly processing various types of films including superhigh-speed films requiring a plurality of film processing steps requiring different reaction times respectively and color films using small quantities of processing solutions. The processing unit is formed by arranging a plurality of pairs of film conveying rollers at given small intervals along an upward concave arc of a circle, closing spaces between the adjacent pairs of film conveying rollers by pairs of sealing rollers, and disposing a pair of support plates provided with ports on the opposite sides of the rollers respectively so as to define processing chambers of small volumes between the adjacent pairs of film conveying rollers and to be arranged successively along the direction of travel of a film (F).
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: June 18, 1996
    Assignee: Hanshin Technical Laboratory, Ltd.
    Inventors: Ryosaku Sawada, Kensaku Sawada, Kosaku Sawada, Sosaku Sawada, Mikio Matsui
  • Patent number: 5426480
    Abstract: A photographic film processing apparatus comprises a water tank for containing a constant quantity of fresh water, and one or a plurality of processing units each comprising a pair of feed rollers disposed with their circumferences in close contact with each other, a pair of delivery rollers spaced apart from the pair of feed rollers and disposed with their circumferences in close contact with each other, a pair of sealing rollers disposed with the circumference of one of them in close contact with the circumferences of the top feed roller and the top delivery roller and with the circumference of the other in close contact with the circumferences of the bottom feed roller and the bottom delivery roller, and a pair of support plates disposed respectively on the opposite sides of the rollers so as to support the rollers for rotation and to define a liquid-tight processing chamber by the circumferences of the rollers and the inner surfaces thereof.
    Type: Grant
    Filed: May 12, 1994
    Date of Patent: June 20, 1995
    Assignee: Hanshin Technical Laboratory, Ltd.
    Inventors: Ryosaku Sawada, Kensaku Sawada, Kosaku Sawada, Sosaku Sawada, Mikio Matsui