Abstract: A solar cell can include a substrate and a semiconductor region disposed in or above the substrate. Selective firing of a conductive paste can be used to form a conductive contact for a solar cell. The solar cell can also include a conductive contact disposed on the semiconductor region with the conductive contact including a conductive paste that has a top and bottom portion with the top portion having particles coalesced together.

Abstract: A solar cell can include a substrate and a semiconductor region disposed in or above the substrate. Selective firing of a conductive paste can be used to form a conductive contact for a solar cell. The solar cell can also include a conductive contact disposed on the semiconductor region with the conductive contact including a conductive paste that has a top and bottom portion with the top portion having particles coalesced together.

Abstract: Methods for forming an ultra thin structure. The method includes a polymer deposition and etching process. In one embodiment, the methods may be utilized to form fabricate submicron structure having a critical dimension less than 30 nm and beyond. The method further includes a multiple etching processes. The processes may be varied to meet different process requirements. In one embodiment, the process gently etches the substrate while shrinking critical dimension of the structures formed within the substrate. The dimension of the structures may be shank by coating a photoresist like polymer to sidewalls of the formed structure, but substantially no polymer accumulation on the bottom surface of the formed structure on the substrate. The embodiments described herein also provide high selectivity in between each layers formed on the substrate during the fabricating process and preserving a good control of profile formed within the structure.

Abstract: A method of filling a gap on a substrate includes providing flows of silicon-containing processing gas oxidizing processing gas, and phosphorous-containing processing gas to a chamber housing the substrate and depositing a first portion of a P-doped silicon oxide film as a substantially conformal layer in the gap by causing a reaction among the processing gases and varying over time a ratio of the gases. The temperature of the substrate is maintained below about 500° C. throughout deposition of the conformal layer. The method also includes depositing a second portion of the P-doped silicon oxide film as a bulk layer by maintaining the ratio of the gases substantially constant throughout deposition of the bulk layer. The temperature of the substrate is maintained below about 500° C. throughout deposition of the bulk layer.

Abstract: A method of operating a substrate processing chamber comprising transferring a first substrate into the substrate processing chamber and heating the substrate to a first temperature of at least 510° C.; depositing an insulating layer over the first substrate while reducing the temperature of the substrate from the first temperature to a second temperature that is lower than the first temperature; transferring the first substrate out of the substrate processing chamber; removing unwanted deposition material formed on interior surfaces of the chamber during the depositing step by introducing reactive halogen species into the chamber while increasing the temperature of chamber; transferring a second substrate into the substrate processing chamber and heating the substrate to the first temperature; and depositing an insulating layer over the second substrate while reducing the temperature of the substrate from the first temperature to the second temperature.

Abstract: A method of filling a gap which is defined by adjacent raised features on a substrate includes providing a flow of a silicon-containing processing gas to a chamber housing the substrate, providing a flow of an oxidizing processing gas to the chamber, and providing a flow of a phosphorous-containing processing gas to the chamber. The method also includes depositing a first portion of a P-doped silicon oxide film as a substantially conformal layer in the gap by causing a reaction between the silicon-containing processing gas, the phosphorous-containing processing gas, and the oxidizing processing gas. Depositing the conformal layer includes varying over time a ratio of the (silicon-containing processing gas plus phosphorous-containing processing gas):(oxidizing processing gas) and maintaining the temperature of the substrate below about 500° C. throughout deposition of the conformal layer. The method also includes depositing a second portion of the P-doped silicon oxide film as a bulk layer.

Abstract: A memory cell with a stored charge on its gate comprising; (A) a channel forming region, (B) a first gate formed on an insulation layer formed on the surface of the channel forming region, the first gate and the channel forming region facing each other through the insulation layer, (C) a second gate capacitively coupled with the first gate, (D) source/drain regions formed in contact with the channel forming region, one source/drain region being spaced from the other, (E) a first non-linear resistance element having two ends, one end being connected to the first gate, and (F) a second non-linear resistance element composed of the first gate, the insulation layer and either the channel-forming region and at least one of the source/drain regions.

Abstract: A semiconductor memory cell comprising a first transistor for readout, a second transistor for switching, and having a first region, a second region formed in a surface region of the first region, a third region formed in a surface region of the second region, a fourth region formed in a surface region of the first region and spaced from the second region, a fifth region formed in a surface region of the fourth region, and a gate region, wherein when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region are nearly symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.

Abstract: A semiconductor memory cell comprising (1) a first transistor of a first conductivity type for read-out having source/drain regions composed of a surface region of a third region and a second region and a channel forming region composed of a surface region of a first region, (2) a second transistor of a second conductivity type for write-in having source/drain regions composed of the first region and a fourth region and a channel forming region composed of a surface region of the third region, and (3) a junction-field-effect transistor of a first conductivity type for current control having gate regions composed of the fourth region and a portion of the first region facing the fourth region, a channel region composed of the third region sandwiched by the fourth region and the first region and source/drain regions composed of the third region.

Abstract: Impurity profiles Pi1 and Ps1 are determined for the same conditions by a reference acquiring means and a simulation capable of producing a result faster than the reference acquiring means, respectively. Errors between the impurity profile Pi1 determined by the reference acquiring means and the impurity profile Ps1 determined by the simulation are determined. An impurity profile Psx is calculated for another kind of conditions by the simulation, and a new impurity profile Psx′ is calculated by correcting the impurity profile Psx so as to reflect the errors.

Abstract: A semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in and a junction-field-effect transistor of the first conductivity type for current control; the first transistor having source/drain regions constituted of a first region and a fourth region, and a channel forming region constituted of a surface region of a third region; the second transistor having source/drain regions constituted of a second region and the third region, and a channel forming region constituted of a surface region of the first region; the junction-field-effect transistor having gate regions constituted of the fifth region and a portion of the third region facing the fifth region, a channel region constituted of part of the fourth region sandwiched by the fifth region and said portion of the third region, and source/drain regions constituted of the fourth region.

Abstract: Provided is a semiconductor memory cell which requires no refreshing operation for retaining information. The semiconductor memory cell comprises a first transistor TR1 having a first conductivity type, a second transistor TR2 having a second conductivity type and a MIS type diode DT for retaining information, wherein one source/drain region of the first transistor TR1 corresponds to the channel forming region CH2 of the second transistor TR2, one source/drain region of the second transistor TR2 corresponds to the channel forming region CH1 of the first transistor TR1, one end of the MIS type diode DT is formed of an extending portion of the channel forming region CH1 of the first transistor TR1, and the other end of the MIS type diode DT is constituted of an electrode which is formed of an electrically conductive material and connected to a third line having a predetermined potential.

Abstract: A memory cell with a stored charge on its gate, comprising (A) a channel forming region, (B) a first gate formed on an insulation layer formed on the surface of the channel forming region, the first gate and the channel forming region facing each other through the insulation layer, (C) a second gate capacitively coupled with the first gate, (D) source/drain regions formed in contact with the channel forming region, one source/drain region being spaced from the other, and (E) a non-linear resistance element having at least two ends with one end connected to the first gate.

Abstract: A semiconductor memory cell includes a read-out transistor of a first conductivity type which has source/drain regions constituted by a second conductive region and a third semiconducting region, a channel forming region constituted by a surface region of a second semiconducting region, and a conductive gate formed on a barrier layer; a switching transistor of a second conductivity type which has source/drain regions constituted by a first conductive region and the second semiconducting region, a channel forming region constituted by a surface region of a first semiconducting region, and a conductive gate formed on a barrier layer; and a current controlling junction-field-effect transistor of a first conductivity type which has gate regions constituted by a third conductive region and a portion of the second semiconducting region, a channel region constituted by a portion of the third semiconducting region, and one source/drain region extended from one end of the channel region, being constituted by a portion

Abstract: A semiconductor memory cell comprising (1) a first transistor of a first conductivity type for read-out having source/drain regions composed of a surface region of a third region and a second region and a channel forming region composed of a surface region of a first region, (2) a second transistor of a second conductivity type for write-in having source/drain regions composed of the first region and a fourth region and a channel forming region composed of a surface region of the third region, and (3) a junction-field-effect transistor of a first conductivity type for current control having gate regions composed of the fourth region and a portion of the first region facing the fourth region, a channel region composed of the third region sandwiched by the fourth region and the first region and source/drain regions composed of the third region.

Abstract: A base is etched using as mask a first masking layer which has been patterned, softened and deformed. Then, the first masking layer is eroded, a second masking layer is selfaligningly formed only on bare portions of the base, and the base is again etched using as mask the second masking layer. Within a pitch of the first masking layer, the base can thus be etched in two regions which are separated from each other. These treatments can also be conducted in two directions.

Abstract: A field effect transistor comprising source and drain regions, a channel region composed of a semiconductor layer formed between the source and drain regions and gate electrodes disposed to at least three surfaces surrounding the channel region. The structure can increase the number of carriers induced in the channel region and enhance the current driving performance and mutual conductance as compared with the single gate structure or double gate structure.

Abstract: A lower-layer interconnection and an upper-layer interconnection formed on the lower-layer interconnection through an interlayer insulating film interposed therebetween are connected to each other by a plurality of contact plugs the interconnections and the contact plugs providing a plurality of conductive paths. The lower-layer interconnection is made of a conductive material having a resistivity higher than the upper-layer interconnection. At least one of the conductive paths provided in the lower-layer interconnections is shorter than the other conductive paths, and the contact plug which provides the shorter conductive path has a lower resistance than the contact plugs which provide the other conductive paths. With this arrangement, the contact plug which provides the shorter conductive path is prevented from suffering an increased current density, and the current densities in the contact plugs are uniformized.

Abstract: A field effect transistor comprising source and drain regions, a channel region composed of a semiconductor layer formed between the source and drain regions and gate electrodes disposed to at least three surfaces surrounding the channel region. The structure can increase the number of carriers induced in the channel region and enhance the current driving performance and mutual conductance as compared with the single gate structure or double gate structure.

Abstract: A method of manufacturing a lateral insulated gate field effect transistor comprises the steps of forming a projecting portion on a first major surface of a semiconductor substrate, forming a pair of gate portions each of which is formed in each side of the projecting portion, forming an insulating layer on the resulting surface of the semiconductor substrate by burying the projecting portion and the pair of gate portions, and removing the semiconductor substrate from a second major surface of the semiconductor substrate to a position of the insulating layer in which the projecting portion is buried to expose the bottom surface of the projecting portion.