Patents by Inventor Mikio Negishi

Mikio Negishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8022551
    Abstract: Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu, or other materials and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: September 20, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tasao Soga, Hanae Shimokawa, Tetsuya Nakatsuka, Kazuma Miura, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh
  • Patent number: 7468294
    Abstract: A semiconductor device comprising semiconductor chips each formed with plural pads at the main surface, chip parts each formed with connection terminals at both ends thereof, a module substrate on which the semiconductor chips and the chip parts are mounted, solder connection portions for connecting the chip parts and the substrate terminals of the module substrate by soldering, gold wires for connecting the pads of the semiconductor chips and corresponding substrate terminals of the module substrate, and a sealing portion formed with a low elasticity resin such as an insulative silicone resin or a low elasticity epoxy resin for covering the semiconductor chips, chip parts, solder connection portions and gold wires which prevents flow out of the solder in the solder connection portion by re-melting thereby preventing short-circuit.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: December 23, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Masashi Yamaura, Hirokazu Nakajima, Nobuyoshi Maejima, Mikio Negishi, Tomio Yamada, Tomomichi Koizumi, Tsuneo Endoh
  • Patent number: 7259465
    Abstract: Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu, etc., and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: August 21, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Tasao Soga, Hanae Shimokawa, Tetsuya Nakatsuka, Kazuma Miura, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh
  • Publication number: 20070031279
    Abstract: Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu, or other materials and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.
    Type: Application
    Filed: April 7, 2006
    Publication date: February 8, 2007
    Applicant: Renesas Technology Corporation
    Inventors: Tasao Soga, Hanae Shimokawa, Tetsuya Nakatsuka, Kazuma Miura, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh
  • Patent number: 7075183
    Abstract: Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu etc. and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: July 11, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Tasao Soga, Hanae Shimokawa, Tetsuya Nakatsuka, Kazuma Miura, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh
  • Publication number: 20060145352
    Abstract: In an electronic device which realizes high-temperature-side solder bonding in temperature-hierarchical bonding, a bonding portion between a semiconductor device and a substrate is formed of metal balls made of Cu, or the like, and compounds formed of metal balls and Sn, and the metal balls are bonded together by the compounds.
    Type: Application
    Filed: January 23, 2006
    Publication date: July 6, 2006
    Applicant: Hitachi, Ltd.
    Inventors: Tasao Soga, Hanae Hata, Tetsuya Nakatsuka, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh
  • Patent number: 7023706
    Abstract: A semiconductor device capable of attaining the reduction of size is disclosed. The semiconductor device comprises a module substrate having a surface and a back surface, a control chip mounted on the surface of the module substrate, plural chip parts mounted on the surface in adjacency to the control chip, first and second output chips mounted on the back surface of the module substrate, plural lands formed on the back surface of the module substrate, and a seal portion formed of resin to seal the control chip and the plural chip parts, wherein the first and second output chips are larger in the amount of heat generated than the control chip, the heat from the first and second output ships is radiated to a mother board, and packaging parts on the surface side of the module substrate are sealed with only a sealing resin without using a metallic case or the like to attain the reduction in size of the module.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: April 4, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Mikio Negishi, Hiroki Noto, Tomio Yamada, Tsuneo Endoh
  • Publication number: 20050082683
    Abstract: A semiconductor device comprising semiconductor chips each formed with plural pads at the main surface, chip parts each formed with connection terminals at both ends thereof, a module substrate on which the semiconductor chips and the chip parts are mounted, solder connection portions for connecting the chip parts and the substrate terminals of the module substrate by soldering, gold wires for connecting the pads of the semiconductor chips and corresponding substrate terminals of the module substrate, and a sealing portion formed with a low elasticity resin such as an insulative silicone resin or a low elasticity epoxy resin for covering the semiconductor chips, chip parts, solder connection portions and gold wires which prevents flow out of the solder in the solder connection portion by re-melting thereby preventing short-circuit.
    Type: Application
    Filed: November 10, 2004
    Publication date: April 21, 2005
    Inventors: Masashi Yamaura, Hirokazu Nakajima, Nobuyoshi Maejima, Mikio Negishi, Tomio Yamada, Tomomichi Koizumi, Tsuneo Endoh
  • Patent number: 6872465
    Abstract: In a solder that realizes high-temperature-side solder bonding in temperature-hierarchical bonding, a connection portion between a semiconductor device and a substrate is formed of metal balls made of Cu or the like and compounds formed of metal balls and Sn, and the metal balls are bonded together by the compounds.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: March 29, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Tasao Soga, Hanae Hata, Tetsuya Nakatsuka, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh
  • Publication number: 20050029666
    Abstract: A semiconductor device, in which a solder layer bonding chip parts and wiring members are enclosed with the resin layer, and the solder layer is comprised of a compound body in which metal powder is distributed in the matrix metal, is disclosed. When a semiconductor device in which the chip parts are installed in the wiring member with the solders, the soldering part is sealed with the resin is mounted secondly on the external wiring member, the outflow of the solders and the short circuit due to the outflow, the disconnections, and the displacement of the chip parts can be prevented.
    Type: Application
    Filed: August 27, 2002
    Publication date: February 10, 2005
    Inventors: Yasutoshi Kurihara, Yoshimasa Takahashi, Tsuneo Endoh, Mikio Negishi, Masashi Yamaura, Hirokazu Nakajima, Yosuke Sakurai, Hironori Kodama
  • Patent number: 6831360
    Abstract: A semiconductor device comprising semiconductor chips each formed with plural pads at the main surface, chip parts each formed with connection terminals at both ends thereof, a module substrate on which the semiconductor chips and the chip parts are mounted, solder connection portions for connecting the chip parts and the substrate terminals of the module substrate by soldering, gold wires for connecting the pads of the semiconductor chips and corresponding substrate terminals of the module substrate, and a sealing portion formed with a low elasticity resin such as an insulative silicone resin or a low elasticity epoxy resin for covering the semiconductor chips, chip parts, solder connection portions and gold wires which prevents flow out of the solder in the solder connection portion by re-melting thereby preventing short-circuit.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: December 14, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Masashi Yamaura, Hirokazu Nakajima, Nobuyoshi Maejima, Mikio Negishi, Tomio Yamada, Tomomichi Koizumi, Tsuneo Endoh
  • Publication number: 20040007384
    Abstract: In an electronic device which realizes high-temperature-side solder bonding in temperature-hierarchical bonding, a bonding portion between a semiconductor device and a substrate is formed of metal balls made of Cu, or the like, and compounds formed of metal balls and Sn, and the metal balls are bonded together by the compounds.
    Type: Application
    Filed: March 7, 2003
    Publication date: January 15, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Tasao Soga, Hanae Hata, Tetsuya Nakatsuka, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh
  • Publication number: 20030224197
    Abstract: In a solder that realizes high-temperature-side solder bonding in temperature-hierarchical bonding, a connection portion between a semiconductor device and a substrate is formed of metal balls made of Cu or the like and compounds formed of metal balls and Sn, and the metal balls are bonded together by the compounds.
    Type: Application
    Filed: March 7, 2003
    Publication date: December 4, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Tasao Soga, Hanae Hata, Tetsuya Nakatsuka, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh
  • Publication number: 20030165052
    Abstract: A semiconductor device capable of attaining the reduction of size is disclosed. The semiconductor device comprises a module substrate having a surface and a back surface, a control chip mounted on the surface of the module substrate, plural chip parts mounted on the surface in adjacency to the control chip, first and second output chips mounted on the back surface of the module substrate, plural lands formed on the back surface of the module substrate, and a seal portion formed of resin to seal the control chip and the plural chip parts, wherein the first and second output chips are larger in the amount of heat generated than the control chip, the heat from the first and second output ships is radiated to a mother board, and packaging parts on the surface side of the module substrate are sealed with only a sealing resin without using a metallic case or the like to attain the reduction in size of the module.
    Type: Application
    Filed: December 20, 2002
    Publication date: September 4, 2003
    Inventors: Mikio Negishi, Hiroki Noto, Tomio Yamada, Tsuneo Endoh
  • Publication number: 20020171157
    Abstract: Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu etc. and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.
    Type: Application
    Filed: June 13, 2001
    Publication date: November 21, 2002
    Inventors: Tasao Soga, Hanae Shimokawa, Tetsuya Nakatsuka, Kazuma Miura, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh
  • Publication number: 20020114726
    Abstract: Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu, or other materials and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.
    Type: Application
    Filed: March 22, 2002
    Publication date: August 22, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Tasao Soga, Hanae Shimokawa, Tetsuya Nakatsuka, Kazuma Miura, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh
  • Publication number: 20020100986
    Abstract: Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu, etc., and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.
    Type: Application
    Filed: March 22, 2002
    Publication date: August 1, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Tasao Soga, Hanae Shimokawa, Tetsuya Nakatsuka, Kazuma Miura, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh
  • Publication number: 20020089052
    Abstract: A semiconductor device comprising semiconductor chips each formed with plural pads at the main surface, chip parts each formed with connection terminals at both ends thereof, a module substrate on which the semiconductor chips and the chip parts are mounted, solder connection portions for connecting the chip parts and the substrate terminals of the module substrate by soldering, gold wires for connecting the pads of the semiconductor chips and corresponding substrate terminals of the module substrate, and a sealing portion formed with a low elasticity resin such as an insulative silicone resin or a low elasticity epoxy resin for covering the semiconductor chips, chip parts, solder connection portions and gold wires which prevents flow out of the solder in the solder connection portion by re-melting thereby preventing short-circuit.
    Type: Application
    Filed: December 19, 2001
    Publication date: July 11, 2002
    Inventors: Masashi Yamaura, Hirokazu Nakajima, Nobuyoshi Maejima, Mikio Negishi, Tomio Yamada, Tomomichi Koizumi, Tsuneo Endoh