Abstract: A semiconductor integrated circuit includes a semiconductor substrate on which an oscillation circuit that generates an oscillation signal by oscillating a resonation element, and a plurality of output circuits that outputs signals based on the oscillation signal, are integrated. A package contains the semiconductor integrated circuit and the resonation element. In the semiconductor integrated circuit, an operation of a first output circuit and an operation of a second output circuit, among a plurality of output circuits, are controlled independently from each other.

Abstract: A semiconductor integrated circuit includes a semiconductor substrate on which an oscillation circuit that generates an oscillation signal by oscillating a resonation element, and a plurality of output circuits that outputs signals based on the oscillation signal, are integrated. A package contains the semiconductor integrated circuit and the resonation element. In the semiconductor integrated circuit, an operation of a first output circuit and an operation of a second output circuit, among a plurality of output circuits, are controlled independently from each other.

Abstract: A phase locked circuit includes a locked loop circuit having a phase comparator, a voltage controlled oscillator, and a variable frequency divider which divides a clock signal fvco output from the voltage controlled oscillator by n and outputs it. Additionally, the phase locked circuit includes a band pass filter part which is coupled to an output side of the voltage controlled oscillator via a switching part. A frequency division ratio setting signal to be input into the variable frequency divider is input as a switching signal into the switching part so as to switch a frequency of the clock signal fvco output from the voltage controlled oscillator. As synchronizing with switching of the frequency, the switching part switches a plurality of band pass filters provided to the band pass filter part and couples to the voltage controlled oscillator.

Abstract: The present invention provides a signal transmission device in which jitter occurring in a clock signal is eliminated. The signal transmission device has a construction in which a transmission end IC chip provided with a transmission part of a data signal and a reception end IC chip provided with a reception part of the data signal, the transmission part and the reception part are connected via a data signal transmission line, an oscillator that outputs a clock signal to the transmission part is connected with the transmission end IC chip, a clock signal transmission line is provided which leads the clock signal output from the oscillator to the reception part, and a SAW filter is arranged in the clock signal transmission line.

Abstract: A phase locked circuit includes a locked loop circuit having a phase comparator, a voltage controlled oscillator, and a variable frequency divider which divides a clock signal fvco output from the voltage controlled oscillator by n and outputs it. Additionally, the phase locked circuit includes a band pass filter part which is coupled to an output side of the voltage controlled oscillator via a switching part. A frequency division ratio setting signal to be input into the variable frequency divider is input as a switching signal into the switching part so as to switch a frequency of the clock signal fvco output from the voltage controlled oscillator. As synchronizing with switching of the frequency, the switching part switches a plurality of band pass filters provided to the band pass filter part and couples to the voltage controlled oscillator.

Abstract: The present invention provides a signal transmission device in which jitter occurring in a clock signal is eliminated. The signal transmission device has a construction in which a transmission end IC chip provided with a transmission part of a data signal and a reception end IC chip provided with a reception part of the data signal, the transmission part and the reception part are connected via a data signal transmission line, an oscillator that outputs a clock signal to the transmission part is connected with the transmission end IC chip, a clock signal transmission line is provided which leads the clock signal output from the oscillator to the reception part, and a SAW filter is arranged in the clock signal transmission line.

Abstract: An oscillator circuit having a first programmable divider for obtaining a reference signal by dividing the frequency of an oscillation signal of a piezoelectric resonator by a frequency dividing number, M. A PLL circuit using the reference signal as input thereto to obtain a multiplied signal, the multiplied signal being formed by multiplying the input signal by a second frequency dividing number N for a second programmable divider provided in a feedback circuit. A third programmable divider capable of dividing the frequency of the multiplied signal by a third frequency dividing number X and outputting the frequency-divided signal. The frequency dividing numbers M, N, and X can be set to values independent of each other. Therefore, innumerable combinations of the frequency dividing numbers M, N, and X can be used and the number of frequencies producible by one oscillator can be largely increased by enabling selection of any suitable one of such combinations.

Abstract: An oscillator circuit having a first programmable divider for obtaining a reference signal by dividing the frequency of an oscillation signal of a piezoelectric resonator by a frequency dividing number M. A PLL circuit using the reference signal as input thereto to obtain a multiplied signal, the multiplied signal being formed by multiplying the input signal by a second frequency dividing number N for a second programmable divider provided in a feedback circuit. A third programmable divider capable of dividing the frequency of the multiplied signal by a third frequency dividing number X and outputting the frequency-divided signal. The frequency dividing numbers M, N, and X can be set to values independent of each other. Therefore, innumerable combinations of the frequency dividing numbers M, N, and X can be used and the number of frequencies producible by one oscillator can be largely increased by enabling selection of any suitable one of such combinations.

Abstract: A PLL (phase locked loop) oscillator suitable as a clock signal source for use in a computer system or the like includes a piezoelectric resonator, an oscillating circuit for generating an oscillating signal in cooperation with the piezoelectric resonator, and a PLL circuit which operates using the oscillating signal generated by the oscillating circuit as a reference signal, all these elements being housed in a package, the frequency of the output signal of the PLL oscillator being determined by the oscillation frequency of the oscillating circuit and the frequency dividing ratio of a programmable frequency divider in the PLL circuit, wherein the frequency dividing ratio of the programmable frequency divider is set by writing the data representing the frequency dividing ratio into a programmable read only memory thereby setting the output frequency to a desired value.

Abstract: A flexible clock and reset signal generation and distribution system and method for distributing a relatively low frequency clock signal to various elements of a computer system that require higher frequency clock signals for operation and includes programmable frequency synthesizers containing phase locked loop (PLL) type frequency multipliers, which are located physically adjacent to the computer system elements for receiving the low frequency clock signal and generating the various required higher frequency clock signals. The source of the relatively low frequency clock signal is a real-time clock (RTC) module having a crystal oscillator, a reset signal generator, and a low voltage detector. The RTC module switches off the low frequency clock signal when the main system power supply falls below a prescribed voltage level, such as, a battery voltage, or a voltage reference, or a combination battery voltage and voltage reference.

Abstract: A piezoelectric oscillator in which radiation of higher harmonic components is reduced. A piezoelectric vibrator and a semiconductor device are provided in an oscillation circuit for making the piezoelectric vibrator oscillate, as is a filter for cutting components in a predetermined frequency band or higher harmonic components of an oscillation signal outputted from the semiconductor device. The piezoelectric vibrator, the semiconductor device and the filter are packed in one package. Radiation of the higher harmonic components is reduced by placing the filter close to the oscillator, by providing a shielding or by operating portions of the oscillator output circuit with a reduced supply voltage.

Abstract: A radio transceiver having digitally-corrected temperature-compensated crystal oscillators (DTCXOs) including digital frequency temperature compensation circuits that are temporarily suspended from being updated, such that temperature compensation updates that can generate noise during periods of reception and transmission that could interfere with the audio channel and/or signal synchronization will be postponed. Temperature is converted to a digital signal that is then used to address a PROM. The PROM outputs a correction word appropriate for the temperature reading and inputs this to a latch. A timing control loads the latch after data has settled. The latched correction word is connected to a bank of switches and capacitors that trim the frequency of the crystal oscillator. During radio transmission and/or reception, the latch will be suspended from loading any new correction words. The last valid correction word, however, will remain.

Abstract: A radio transceiver having digitally-corrected temperature-compensated crystal oscillators (DTCXOs) including digital frequency temperature compensation circuits that are temporarily suspended from being updated, such that temperature compensation updates that can generate noise during periods of reception and transmission that could interfere with the audio channel and/or signal synchronization will be postponed. Temperature is converted to a digital signal that is then used to address a PROM. The PROM outputs a correction word appropriate for the temperature reading and inputs this to a latch. A timing control loads the latch after data has settled. The latched correction word is connected to a bank of switches and capacitors that trim the frequency of the crystal oscillator. During radio transmission and/or reception, the latch will be suspended from loading any new correction words. The last valid correction word, however, will remain.