Patents by Inventor Mikito Sakakibara
Mikito Sakakibara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6627956Abstract: A semiconductor switching device of mirror logic includes two FETs having a gate width of 600 &mgr;m, a common input terminal, two control terminal and two output terminals. The resistors connecting the control terminals and the gate electrodes of FETs are placed underneath a pad metal layer extending from the common input terminal. Both FETs extend into the space between the control terminals and the output terminals. The device can be housed in the same package as the device of non-mirror logic.Type: GrantFiled: June 7, 2002Date of Patent: September 30, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Toshikazu Hirai, Mikito Sakakibara
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Patent number: 6627967Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: GrantFiled: July 26, 2002Date of Patent: September 30, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Katsuaki Onada, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20030151137Abstract: A semiconductor chip is mounted on a wiring board that has a two-layer lead structure. One of the leads used for receiving input signals is disposed on the lower layer and runs underneath the semiconductor chip forming an U-shaped wiring line while other leads are disposed on the upper layer. Because one of the upper layer leads for receiving input signals is disposed in the U-shaped pocket of the U-shaped wiring line of the lower layer, the relative positioning of corresponding terminals can be changed into a reversal of the positioning of the electrode pads of the chip connected to the terminals. Furthermore, one of the upper layer lead for receiving control signals is placed between the chip and the lower layer lead underneath the chip to prevent high frequency signal interference.Type: ApplicationFiled: December 5, 2002Publication date: August 14, 2003Applicant: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Mikito Sakakibara, Hideyuki Inotsume, Haruhiko Sakai, Shigeo Kimura
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Publication number: 20030137044Abstract: Two different switches with two different signal input schemes are fabricated by mounting the same semiconductor chip on the same lead pattern. Two of the leads of the lead pattern provides space enough for wire-bonding connection to corresponding electrode pads on the semiconductor chip at both ends of the semiconductor chip. Because each of electrode pads can be connected to the corresponding lead at either end of the semiconductor chip, two sets of bonding wire connection between the leads and the electrode pads provides two different switches with two different signal inputs scheme.Type: ApplicationFiled: November 15, 2002Publication date: July 24, 2003Inventors: Tetsuro Asano, Mikito Sakakibara, Hideyuki Inotsume, Haruhiko Sakai, Shigeo Kimura
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Publication number: 20030129788Abstract: In a method of manufacturing a compound semiconductor device, individual chip patterns are projected onto a (100) surface of a GaAs wafer so that the columns and rows of the chip patterns are aligned in a direction slanting by 45 degrees with respect to a [O11] direction of the GaAs wafer. The wafer is diced along this slanting direction and chipping along the edges of the individual separated chips is greatly reduced.Type: ApplicationFiled: December 26, 2002Publication date: July 10, 2003Applicant: SANYO ELECTRIC CO., LTD.Inventors: Tetsuro Asano, Masahiro Uekawa, Koichi Hirata, Mikito Sakakibara
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Patent number: 6580107Abstract: The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 &mgr;m for obtaining a proper isolation between them. The overall chip size is reduced, first, by reducing the gate width of the switching FET operating at frequencies above 2.4 GHz to 700 &mgr;m or smaller together with the omission of the shunt FET, and, then, by reducing the separation between the connecting pad and the circuit wiring to 20 &mgr;m or smaller. This reduction of the separation is made possible by the introduction of an insulating film and a impurity region between the outermost portion of the connecting pad and the substrate for preventing the extension of the depletion layer.Type: GrantFiled: October 10, 2001Date of Patent: June 17, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Toshikazu Hirai, Takayoshi Higashino, Koichi Hirata, Mikito Sakakibara
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Patent number: 6573529Abstract: A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. A signal transmitting FET has a gate width of 500 &mgr;m and a signal receiving FET has a gate width of 400 &mgr;m. A resistor connecting a gate electrode and a control terminal of the signal transmitting FET is tightly configured to provide expanding space for the FET. Despite the reduced size, the switching device can allow a maximum power of 22.5 dBm to pass through because of the asymmetrical device design. The switching device operates at frequencies of 2.4 GHz or higher without use of shunt FET.Type: GrantFiled: May 24, 2002Date of Patent: June 3, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Toshikazu Hirai, Mikito Sakakibara
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Publication number: 20030094668Abstract: An integrated Schottky barrier diode chip includes a compound semiconductor substrate, a plurality of Schottky barrier diodes formed on the substrate and an insulating region formed on the substrate by an on implantation. The insulating region electrically separates a portion of a diode at a cathode voltage from a portion of the diode at an anode voltage. Because of the absence of a polyimide layer and trench structures, this planar device configuration results in simpler manufacturing method and improved device characteristics.Type: ApplicationFiled: October 30, 2002Publication date: May 22, 2003Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20030094679Abstract: A semiconductor device includes four input terminals, four leads extending from the corresponding input terminals and a semiconductor chip that has a first circuit and a second circuit and is mounted on one of the leads. The lead having the semiconductor chip thereon bends in a plane of the substrate so that an end portion and a mid portion of the lead are exposed on one side of the semiconductor chip. One of the input electrode pads of the first circuit is connected to the end portion of the lead by a bonding wire. The end portion of the lead is on the opposite side of the rmid portion of the lead with respect to one of the leads that is connected to one of the input electrode pads of the second circuit by a bonding wire. This configuration achieves a crossing wiring structure within the packaging. By changing the connection of bonding wires, the crossing wiring structure is easily undone.Type: ApplicationFiled: October 30, 2002Publication date: May 22, 2003Inventors: Tetsuro Asano, Mikito Sakakibara, Hideyuki Inotsume, Haruhiko Sakai, Shigeo Kimura
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Publication number: 20030089959Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: ApplicationFiled: July 26, 2002Publication date: May 15, 2003Applicant: Sanyo Electric Company, Ltd.Inventors: Tetsuro Asano, Katsuaki Onada, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20030060031Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: ApplicationFiled: July 26, 2002Publication date: March 27, 2003Applicant: Sanyo Electric Company, Ltd.Inventors: Tetsuro Asano, Katsuaki Onada, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20030036252Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: ApplicationFiled: July 26, 2002Publication date: February 20, 2003Applicant: Sanyo Electric Company, Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20030025175Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: ApplicationFiled: July 26, 2002Publication date: February 6, 2003Applicant: Sanyo Electric Company, Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20030017644Abstract: In a method of manufacturing a compound semiconductor device, individual chip patterns are projected onto a (1 0 0) surface of a GaAs wafer so that the columns and rows of the chip patterns are aligned in a direction slanting by 45 degrees with respect to a [O 1 1] direction of the GaAs wafer. The wafer is diced along this slanting direction and chipping along the edges of the individual separated chips is greatly reduced.Type: ApplicationFiled: July 8, 2002Publication date: January 23, 2003Applicant: SANYO ELECTRIC CO., LTD.Inventors: Tetsuro Asano, Masahiro Uekawa, Koichi Hirata, Mikito Sakakibara
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Publication number: 20030013240Abstract: In a method of manufacturing a compound semiconductor device, individual chip patterns are projected onto a (1 0 0) surface of a GaAs wafer so that the columns and rows of the chip patterns are aligned in a direction slanting by 45 degrees with respect to a [0 1 1] direction of the GaAs wafer. The wafer is diced along this slanting direction and chipping along the edges of the individual separated chips is greatly reduced.Type: ApplicationFiled: July 8, 2002Publication date: January 16, 2003Applicant: SANYO ELECTRIC CO., LTD.Inventors: Tetsuro Asano, Masahiro Uekawa, Koichi Hirata, Mikito Sakakibara
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Publication number: 20030013276Abstract: A local oscillation FET has a source connecting pad, a drain connecting pad and a gate connecting pad. The source connecting pad occupies one comer of a substrate, and the drain and gate connecting pads are placed at the neighboring comers so that the three connecting pads form an L shape on the substrate. As a modification to this configuration, another source connecting pad is placed at the remaining comer of the substrate so that the drain and gate connecting pads are shielded from each other by the two source connecting pads. These device configurations contribute to size reduction of the local oscillation FET.Type: ApplicationFiled: June 24, 2002Publication date: January 16, 2003Applicant: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Masahiro Uekawa, Koichi Hirata, Mikito Sakakibara
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Publication number: 20020195617Abstract: The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 &mgr;m for obtaining a proper isolation between them. The overall chip size is reduced, first, by reducing the gate width of the switching FET operating at frequencies above 2.4 GHz to 700 &mgr;m or smaller together with the omission of the shunt FET, and, then, by reducing the separation between the connecting pad and the circuit wiring to 20 &mgr;m or smaller. This reduction of the separation is made possible by the introduction of an insulating film and a impurity region between the outermost portion of the connecting pad and the substrate for preventing the extension of the depletion layer.Type: ApplicationFiled: August 5, 2002Publication date: December 26, 2002Inventors: Tetsuro Asano, Toshikazu Hirai, Takayoshi Higashino, Koichi Hirata, Mikito Sakakibara
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Publication number: 20020185667Abstract: A semiconductor switching device of mirror logic includes two FETs having a gate width of 600 &mgr;m, a common input terminal, two control terminal and two output terminals. The resistors connecting the control terminals and the gate electrodes of FETs are placed underneath a pad metal layer extending from the common input terminal. Both FETs extend into the space between the control terminals and the output terminals. The device can be housed in the same package as the device of non-mirror logic.Type: ApplicationFiled: June 7, 2002Publication date: December 12, 2002Applicant: SANYO ELECTRIC CO., LTD.Inventors: Tetsuro Asano, Toshikazu Hirai, Mikito Sakakibara
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Publication number: 20020187755Abstract: A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. A signal transmitting FET has a gate width of 500 &mgr;m and a signal receiving FET has a gate width of 400 &mgr;m. A resistor connecting a gate electrode and a control terminal of the signal transmitting FET is tightly configured to provide expanding space for the FET. Despite the reduced size, the switching device can allow a maximum power of 22.5 dBm to pass through because of the asymmetrical device design. The switching device operates at frequencies of 2.4 GHz or higher without use of shunt FET.Type: ApplicationFiled: May 24, 2002Publication date: December 12, 2002Applicant: SANYO ELECTRIC CO., LTD.Inventors: Tetsuro Asano, Toshikazu Hirai, Mikito Sakakibara
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Publication number: 20020179981Abstract: A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. A signal transmitting FET has a gate width of 500 &mgr;m and a signal receiving FET has a gate width of 400 &mgr;m. A resistor connecting a gate electrode and a control terminal of the signal transmitting FET is tightly configured to provide expanding space for the FET. Despite the reduced size, the switching device can allow a maximum power of 22.5 dBm to pass through because of the asymmetrical device design. The switching device operates at frequencies of 2.4 GHz or higher without use of shunt FET.Type: ApplicationFiled: May 24, 2002Publication date: December 5, 2002Applicant: SANYO ELECTRIC CO., LTD.Inventors: Tetsuro Asano, Toshikazu Hirai, Mikito Sakakibara