Patents by Inventor Mikiya Uchida
Mikiya Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8115241Abstract: A semiconductor device of the present invention includes a substrate; an imaging region which is formed at part of the substrate and in which photoelectric conversion cells including photoelectric conversion sections are arranged in the form of an array; a control-circuit region which is formed at part of the substrate and in which the imaging region is controlled and a signal from the imaging region is outputted; and a copper-containing interconnect layer formed above the substrate and made of a material containing copper. Furthermore, a first anti-diffusion layer and a second anti-diffusion layer are formed, as anti-diffusion layers for preventing the copper from diffusing into each photoelectric conversion section, on the photoelectric conversion section and the copper-containing interconnect layer, respectively.Type: GrantFiled: September 18, 2008Date of Patent: February 14, 2012Assignee: Panasonic CorporationInventors: Mitsuyoshi Mori, Mikiya Uchida, Kazuo Fujiwara, Takumi Yamaguchi
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Patent number: 7928485Abstract: A solid-state imaging apparatus includes a plurality of photosensitive cells, and a driving unit provided for driving the plurality of photosensitive cells. Each photosensitive cell includes a photodiode formed to be exposed on a surface of a semiconductor substrate for the purpose of accumulating signal charge obtained by subjecting incident light to photoelectric conversion, a transfer transistor for transferring signal charge accumulated by the photodiode, a floating diffusion layer for temporarily accumulating signal charge transferred by the transfer transistor, and an amplifier transistor for amplifying signal charge temporarily accumulated in the floating diffusion layer. A source/drain diffusion layer provided in the amplifier transistor is covered with a salicide layer, and the floating diffusion layer is formed to be exposed on a surface of the semiconductor substrate.Type: GrantFiled: October 27, 2008Date of Patent: April 19, 2011Assignee: Panasonic CorporationInventors: Mikiya Uchida, Yoshiyuki Matsunaga, Makoto Inagaki
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Patent number: 7851867Abstract: An integrated circuit includes: a semiconductor substrate that has a well region containing a first conductivity type impurity; and an enhancement type MOS transistor and a plurality of depletion type MOS transistors, each of which is formed in the well region and has a channel region under a gate electrode. At least one of the depletion type MOS transistors has, in the channel region, an implantation region into which a second conductivity type impurity is implanted so that a threshold voltage is adjusted. The implantation region has the first conductivity type impurity and the second conductivity type impurity. Further, the second conductivity type impurity has a concentration that is higher than a concentration of the first conductivity type impurity.Type: GrantFiled: November 21, 2006Date of Patent: December 14, 2010Assignee: Panasonic CorporationInventors: Chinatsu Seto, Mikiya Uchida, Kenichi Mimuro, Emi Kanazaki
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Patent number: 7847848Abstract: In a MOS-type solid-state imaging device 1, in pixels 101 to 104 in which lines in an upper layer (charge transfer lines 1018 to 1048) are formed in shifted positions located toward a center L1 of an image area, each two oppositely disposed pixels with the center L1 of the image area sandwiched therebetween, such as a pixel 101 and a pixel 104 have the following relation. In each of the pixels 101 and 104, power supply lines 1016 and 1046, vertical signal lines 1017 and 1047, and charge transfer lines 1018 and 1048 relating to each of the pixels 101 and 104 are arranged symmetrically with respect to an imaginary plane extending from the center L1 of a sensor 10 in a direction orthogonal to the drawing page in an X-axis direction.Type: GrantFiled: January 4, 2008Date of Patent: December 7, 2010Assignee: Panasonic CorporationInventors: Hirohisa Ohtsuki, Ryohei Miyagawa, Motonari Katsuno, Mikiya Uchida
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Patent number: 7800144Abstract: A semiconductor device of the present invention includes a substrate; an imaging region which is formed at part of the substrate and in which photoelectric conversion cells including photoelectric conversion sections are arranged in the form of an array; a control-circuit region which is formed at part of the substrate and in which the imaging region is controlled and a signal from the imaging region is outputted; and a copper-containing interconnect layer formed above the substrate and made of a material containing copper. Furthermore, a first anti-diffusion layer and a second anti-diffusion layer are formed, as anti-diffusion layers for preventing the copper from diffusing into each photoelectric conversion section, on the photoelectric conversion section and the copper-containing interconnect layer, respectively.Type: GrantFiled: September 18, 2008Date of Patent: September 21, 2010Assignee: Panasonic CorporationInventors: Mitsuyoshi Mori, Mikiya Uchida, Kazuo Fujiwara, Takumi Yamaguchi
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Patent number: 7755150Abstract: An N-type epitaxial layer 115, which is formed above an N-type semiconductor substrate 114 in each of a pixel region and a peripheral circuit region; a first P-type well 1 formed above the N-type epitaxial layer 115 in the pixel region; and light receiving regions 117, which are formed within the first P-type well 1 and each of which is a component of a photodiode, are included. The peripheral circuit region includes: second P-type wells 2, which are formed from a surface 200 of the peripheral circuit region to a desired depth and each of which is a component of an N-Channel MOS transistor; an N-type well 3 which is formed from the surface 200 of the peripheral circuit region to a desired depth and which is a component of a P-Channel MOS transistor; and a third P-type well 4 which is formed so as to have such a shape as to isolate the N-type well 3 from the N-type epitaxial layer 115 and which has a higher impurity concentration than that of the first P-type well 1.Type: GrantFiled: June 6, 2007Date of Patent: July 13, 2010Assignee: Panasonic CorporationInventors: Emi Ohtsuka, Mikiya Uchida, Ryohei Miyagawa
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Patent number: 7675327Abstract: The semiconductor device of the present invention includes a bootstrap circuit, the bootstrap circuit including: a selection transistor composed of an n-channel MOS transistor; a booster transistor of which a gate is connected to a drain of the selection transistor; and a boosting circuit that is connected between the gate and a source of the booster transistor, and boosts gate voltage with respect to the source of the booster transistor, wherein gate dimensions of the selection transistor are smaller than gate dimensions of the booster transistor. According to this configuration, the semiconductor device can realize increasing an action of a circuit, decreasing a chip size and simplifying processes.Type: GrantFiled: May 12, 2006Date of Patent: March 9, 2010Assignee: Panasonic CorporationInventors: Ken Mimuro, Mikiya Uchida
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Patent number: 7563635Abstract: In the present invention, an etching hole 21 is formed in a polysilicon film 14 as a cavity-wall member. Through the etching hole 21, hydrofluoric acid is injected, so as to dissolve a silicon oxide film 13, thereby forming a cavity 22. In the cavity 22, a detecting unit 12 of a sensor is in an exposed condition. Next, by sputtering, an Al film 16 is deposited in the etching hole 21 and on an upper face of a substrate. Thereafter, a portion of the Al film 16 positioned on the polysilicon film 14 is removed by etching back, thereby leaving only a metal closure 16a of Al which closes the etching hole. The sputtering step is performed under a pressure of 5 Pa or less, so that the pressure in the cavity can be held to be low.Type: GrantFiled: August 15, 2007Date of Patent: July 21, 2009Assignee: Panasonic CorporationInventors: Kimiya Ikushima, Hiroyoshi Komobuchi, Asako Baba, Mikiya Uchida
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Patent number: 7550814Abstract: A solid-state imaging device including: a plurality of photosensitive cells, each having a photodiode, arranged on a semiconductor substrate (1) in a matrix; and a peripheral driving circuit that has a plurality of transistors for driving the plurality of photosensitive cells. The plurality of transistors includes a first transistor and a second transistor, the first transistor having a first diffusion layer (2) as a source or a drain where a signal potential corresponding to a signal charge generated by the photodiode is transmitted and held, and the second transistor having a second diffusion layer as a source and a drain where the signal potential is not transmitted.Type: GrantFiled: October 28, 2005Date of Patent: June 23, 2009Assignee: Panasonic CorporationInventors: Mikiya Uchida, Ken Mimuro, Mototaka Ochi
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Publication number: 20090072125Abstract: A solid-state imaging apparatus includes a plurality of photosensitive cells, and a driving unit provided for driving the plurality of photosensitive cells. Each photosensitive cell includes a photodiode formed to be exposed on a surface of a semiconductor substrate for the purpose of accumulating signal charge obtained by subjecting incident light to photoelectric conversion, a transfer transistor for transferring signal charge accumulated by the photodiode, a floating diffusion layer for temporarily accumulating signal charge transferred by the transfer transistor, and an amplifier transistor for amplifying signal charge temporarily accumulated in the floating diffusion layer. A source/drain diffusion layer provided in the amplifier transistor is covered with a salicide layer, and the floating diffusion layer is formed to be exposed on a surface of the semiconductor substrate.Type: ApplicationFiled: October 27, 2008Publication date: March 19, 2009Applicant: Panasonic CorporationInventors: Mikiya Uchida, Yoshiyuki Matsunaga, Makoto Inagaki
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Publication number: 20090021626Abstract: A semiconductor device of the present invention includes a substrate; an imaging region which is formed at part of the substrate and in which photoelectric conversion cells including photoelectric conversion sections are arranged in the form of an array; a control-circuit region which is formed at part of the substrate and in which the imaging region is controlled and a signal from the imaging region is outputted; and a copper-containing interconnect layer formed above the substrate and made of a material containing copper. Furthermore, a first anti-diffusion layer and a second anti-diffusion layer are formed, as anti-diffusion layers for preventing the copper from diffusing into each photoelectric conversion section, on the photoelectric conversion section and the copper-containing interconnect layer, respectively.Type: ApplicationFiled: September 18, 2008Publication date: January 22, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Mitsuyoshi MORI, Mikiya Uchida, Kazuo Fujiwara, Takumi Yamaguchi
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Publication number: 20090014759Abstract: A semiconductor device of the present invention includes a substrate; an imaging region which is formed at part of the substrate and in which photoelectric conversion cells including photoelectric conversion sections are arranged in the form of an array; a control-circuit region which is formed at part of the substrate and in which the imaging region is controlled and a signal from the imaging region is outputted; and a copper-containing interconnect layer formed above the substrate and made of a material containing copper. Furthermore, a first anti-diffusion layer and a second anti-diffusion layer are formed, as anti-diffusion layers for preventing the copper from diffusing into each photoelectric conversion section, on the photoelectric conversion section and the copper-containing interconnect layer, respectively.Type: ApplicationFiled: September 18, 2008Publication date: January 15, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Mitsuyoshi MORI, Mikiya Uchida, Kazuo Fujiwara, Takumi Yamaguchi
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Patent number: 7459335Abstract: A solid-state imaging apparatus includes a plurality of photosensitive cells, and a driving unit provided for driving the plurality of photosensitive cells. Each photosensitive cell includes a photodiode formed to be exposed on a surface of a semiconductor substrate for the purpose of accumulating signal charge obtained by subjecting incident light to photoelectric conversion, a transfer transistor for transferring signal charge accumulated by the photodiode, a floating diffusion layer for temporarily accumulating signal charge transferred by the transfer transistor, and an amplifier transistor for amplifying signal charge temporarily accumulated in the floating diffusion layer. A source/drain diffusion layer provided in the amplifier transistor is covered with a salicide layer, and the floating diffusion layer is formed to be exposed on a surface of the semiconductor substrate.Type: GrantFiled: March 22, 2007Date of Patent: December 2, 2008Assignee: Panasonic CorporationInventors: Mikiya Uchida, Yoshiyuki Matsunaga, Makoto Inagaki
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Publication number: 20080278614Abstract: In a MOS-type solid-state imaging device 1, in pixels 101 to 104 in which lines in an upper layer (charge transfer lines 1018 to 1048) are formed in shifted positions located toward a center L1 of an image area, each two oppositely disposed pixels with the center L1 of the image area sandwiched therebetween, such as a pixel 101 and a pixel 104 have the following relation. In each of the pixels 101 and 104, power supply lines 1016 and 1046, vertical signal lines 1017 and 1047, and charge transfer lines 1018 and 1048 relating to each of the pixels 101 and 104 are arranged symmetrically with respect to an imaginary plane extending from the center L1 of a sensor 10 in a direction orthogonal to the drawing page in an X-axis direction.Type: ApplicationFiled: January 4, 2008Publication date: November 13, 2008Inventors: Hirohisa OHTSUKI, Ryohei MIYAGAWA, Motonari KATSUNO, Mikiya UCHIDA
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Patent number: 7436012Abstract: A semiconductor device of the present invention includes a substrate; an imaging region which is formed at part of the substrate and in which photoelectric conversion cells including photoelectric conversion sections are arranged in the form of an array; a control-circuit region which is formed at part of the substrate and in which the imaging region is controlled and a signal from the imaging region is outputted; and a copper-containing interconnect layer formed above the substrate and made of a material containing copper. Furthermore, a first anti-diffusion layer and a second anti-diffusion layer are formed, as anti-diffusion layers for preventing the copper from diffusing into each photoelectric conversion section, on the photoelectric conversion section and the copper-containing interconnect layer, respectively.Type: GrantFiled: January 20, 2006Date of Patent: October 14, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mitsuyoshi Mori, Mikiya Uchida, Kazuo Fujiwara, Takumi Yamaguchi
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Patent number: 7364932Abstract: In the present invention, an etching hole 21 is formed in a polysilicon film 14 as a cavity-wall member. Through the etching hole 21, hydrofluoric acid is injected, so as to dissolve a silicon oxide film 13, thereby forming a cavity 22. In the cavity 22, a detecting unit 12 of a sensor is in an exposed condition. Next, by sputtering, an Al film 16 is deposited in the etching hole 21 and on an upper face of a substrate. Thereafter, a portion of the Al film 16 positioned on the polysilicon film 14 is removed by etching back, thereby leaving only a metal closure 16a of Al which closes the etching hole. The sputtering step is performed under a pressure of 5 Pa or less, so that the pressure in the cavity can be held to be low.Type: GrantFiled: December 25, 2003Date of Patent: April 29, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kimiya Ikushima, Hiroyoshi Komobuchi, Asako Baba, Mikiya Uchida
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Patent number: 7329557Abstract: A solid-state imaging device includes: a plurality of N-type photodiode regions formed inside a P-type well; a gate electrode having one edge being positioned adjacent to each of the photodiode regions; a N-type drain region positioned adjacent to the other edge of the gate electrode; an element-isolating portion having a STI structure, and a gate oxide film having a thickness of not more than 10 nm. One edge of the gate electrode overlaps the photodiode region.Type: GrantFiled: February 10, 2006Date of Patent: February 12, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ken Mimuro, Mikiya Uchida, Mototaka Ochi
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Publication number: 20070298534Abstract: In the present invention, an etching hole 21 is formed in a polysilicon film 14 as a cavity-wall member. Through the etching hole 21, hydrofluoric acid is injected, so as to dissolve a silicon oxide film 13, thereby forming a cavity 22. In the cavity 22, a detecting unit 12 of a sensor is in an exposed condition. Next, by sputtering, an Al film 16 is deposited in the etching hole 21 and on an upper face of a substrate. Thereafter, a portion of the Al film 16 positioned on the polysilicon film 14 is removed by etching back, thereby leaving only a metal closure 16a of Al which closes the etching hole. The sputtering step is performed under a pressure of 5 Pa or less, so that the pressure in the cavity can be held to be low.Type: ApplicationFiled: August 15, 2007Publication date: December 27, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kimiya IKUSHIMA, Hiroyoshi KOMOBUCHI, Asako BABA, Mikiya UCHIDA
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Publication number: 20070290286Abstract: A solid-state imaging device including: a plurality of photosensitive cells, each having a photodiode, arranged on a semiconductor substrate (1) in a matrix; and a peripheral driving circuit that has a plurality of transistors for driving the plurality of photosensitive cells. The plurality of transistors includes a first transistor and a second transistor, the first transistor having a first diffusion layer (2) as a source or a drain where a signal potential corresponding to a signal charge generated by the photodiode is transmitted and held, and the second transistor having a second diffusion layer as a source and a drain where the signal potential is not transmitted.Type: ApplicationFiled: October 28, 2005Publication date: December 20, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Mikiya Uchida, Ken Mimuro, Mototaka Ochi
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Publication number: 20070284679Abstract: An N-type epitaxial layer 115, which is formed above an N-type semiconductor substrate 114 in each of a pixel region and a peripheral circuit region; a first P-type well 1 formed above the N-type epitaxial layer 115 in the pixel region; and light receiving regions 117, which are formed within the first P-type well land each of which is a component of a photodiode, are included. The peripheral circuit region includes: second P-type wells 2, which are formed from a surface 200 of the peripheral circuit region to a desired depth and each of which is a component of an N-Channel MOS transistor; an N-type well 3 which is formed from the surface 200 of the peripheral circuit region to a desired depth and which is a component of a P-Channel MOS transistor; and a third P-type well 4 which is formed so as to have such a shape as to isolate the N-type well 3 from the N-type epitaxial layer 115 and which has a higher impurity concentration than that of the first P-type well 1.Type: ApplicationFiled: June 6, 2007Publication date: December 13, 2007Inventors: Emi Ohtsuka, Mikiya Uchida, Ryohei Miyagawa