Patents by Inventor Mikko Lintonen
Mikko Lintonen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923805Abstract: An oscillator arrangement is provided, comprising a relaxation oscillator having an active state and an inactive state; a bias current circuit portion arranged to provide a bias current to the relaxation oscillator during said active state; and an electronic switch arranged to isolate said relaxation oscillator from the bias current circuit portion when in said inactive state. The oscillator arrangement is arranged to store an internal voltage value associated with said bias current and the bias current circuit portion is arranged to use the stored internal voltage value to generate the bias current when the oscillator is started up from the inactive state to the active state.Type: GrantFiled: December 11, 2020Date of Patent: March 5, 2024Assignee: Nordic Semiconductor ASAInventors: Mikko Lintonen, Jarmo Väänänen
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Publication number: 20230010430Abstract: An oscillator arrangement is provided, comprising a relaxation oscillator having an active state and an inactive state; a bias current circuit portion arranged to provide a bias current to the relaxation oscillator during said active state; and an electronic switch arranged to isolate said relaxation oscillator from the bias current circuit portion when in said inactive state. The oscillator arrangement is arranged to store an internal voltage value associated with said bias current and the bias current circuit portion is arranged to use the stored internal voltage value to generate the bias current when the oscillator is started up from the inactive state to the active state.Type: ApplicationFiled: December 11, 2020Publication date: January 12, 2023Applicant: Nordic Semiconductor ASAInventors: Mikko LINTONEN, Jarmo VÄÄNÄNEN
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Patent number: 11188111Abstract: A voltage monitoring circuit portion is arranged to monitor a negative supply voltage (Vneg) and comprises a negative voltage generator arranged to generate the negative supply voltage (Vneg) and to output the negative supply voltage (Vneg) at an output terminal. A capacitor is arranged so that a first capacitor plate is connected to the output terminal of the generator and to a reference node via a potential divider. The potential divider is arranged to produce a monitor voltage (Vmonitor) between the resistors, where the reference node is supplied with a positive predetermined reference voltage (Vref). A comparator compares the monitor voltage (Vmonitor) to a threshold voltage (Vref_low) and to produce an output signal having a first value when the monitor voltage (Vmonitor) is below the threshold voltage (Vref_low) and having a second value otherwise. The negative voltage generator is enabled only when the output signal has its second value.Type: GrantFiled: May 1, 2020Date of Patent: November 30, 2021Assignee: Nordic Semiconductor ASAInventors: Mikko Lintonen, Jarmo Väänänen, Janne Juusola
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Publication number: 20200348710Abstract: A voltage monitoring circuit portion is arranged to monitor a negative supply voltage (Vneg) and comprises a negative voltage generator arranged to generate the negative supply voltage (Vneg) and to output the negative supply voltage (Vneg) at an output terminal. A capacitor is arranged so that a first capacitor plate is connected to the output terminal of the generator and to a reference node via a potential divider. The potential divider is arranged to produce a monitor voltage (Vmonitor) between the resistors, where the reference node is supplied with a positive predetermined reference voltage (Vref). A comparator compares the monitor voltage (Vmonitor) to a threshold voltage (Vref_low) and to produce an output signal having a first value when the monitor voltage (Vmonitor) is below the threshold voltage (Vref_low) and having a second value otherwise. The negative voltage generator is enabled only when the output signal has its second value.Type: ApplicationFiled: May 1, 2020Publication date: November 5, 2020Applicant: Nordic Semiconductor ASAInventors: Mikko LINTONEN, Jarmo VÄÄNÄNEN, Janne JUUSOLA
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Patent number: 10678288Abstract: A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable pre-charge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor.Type: GrantFiled: August 30, 2019Date of Patent: June 9, 2020Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Mikko Lintonen, Marko Pessa
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Publication number: 20190384341Abstract: A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable pre-charge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor.Type: ApplicationFiled: August 30, 2019Publication date: December 19, 2019Inventors: Mikko Lintonen, Marko Pessa
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Patent number: 10429875Abstract: A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable pre-charge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor.Type: GrantFiled: February 26, 2018Date of Patent: October 1, 2019Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Mikko Lintonen, Marko Pessa
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Publication number: 20180181156Abstract: A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable pre-charge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor.Type: ApplicationFiled: February 26, 2018Publication date: June 28, 2018Inventors: Mikko Lintonen, Marko Pessa
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Patent number: 9904309Abstract: A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable precharge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor.Type: GrantFiled: May 13, 2015Date of Patent: February 27, 2018Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Mikko Lintonen, Marko Pessa
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Publication number: 20170060163Abstract: A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable precharge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor.Type: ApplicationFiled: May 13, 2015Publication date: March 2, 2017Inventors: Mikko Lintonen, Marko Pessa
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Patent number: 9405308Abstract: A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable pre-charge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor. This limits the current through the first transistor and into the voltage setting circuit for the initial duration.Type: GrantFiled: May 19, 2014Date of Patent: August 2, 2016Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Mikko Lintonen, Marko Pessa
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Publication number: 20150331434Abstract: A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable pre-charge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor.Type: ApplicationFiled: May 19, 2014Publication date: November 19, 2015Applicant: Telefonaktiebolaget L M Ericsson (publ)Inventors: Mikko Lintonen, Marko Pessa
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Patent number: 9118458Abstract: A clock generation circuit is operative to disable and enable a plurality of output clock signals while maintaining predetermined phase relationships between the clock signals. A reference clock signal is divided by a factor of at least two, to generate a master clock signal. A plurality of phase circuits, each independently enabled, generates a plurality of output clock signals by dividing the reference clock signal. The output clock signals have predetermined phase relationships relative to each other. Each phase circuit is enabled synchronously to a synchronization edge of the master clock signal. A synchronization circuit associated with each phase circuit ensures synchronization with the master clock signal by outputting a phase circuit enable signal only upon the conditions of a clock enable signal associated with the output clock being asserted and the receipt of a predetermined number of master clock signal synchronizing edges.Type: GrantFiled: April 24, 2014Date of Patent: August 25, 2015Assignee: Telefonaktiebolaget L M Ericsson (publ)Inventors: Mikko Lintonen, Jukka Kohola, Marko Pessa, Olli Varkki
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Publication number: 20150222330Abstract: In a wireless power charger a receiver (6) is inductively coupled to a transmitter (1) to receive power for charging an accumulator in a device (11). The receiver (6) communicates charging data to the transmitter (1) by imposing current pulses across the direct current output terminals of a rectifier (9) in the receiver. To enhance the performance of the receiver without reducing the signal to noise ratio of the current pulse receiver to transmitter communication the shape of unwanted transient currents in a filter capacitor (10) are sensed and the transient current shape added to an ideal rectangular step function pulse shape to produce a communication pulse shape. As a result the communication pulse shape seen at a secondary inductor (7) of the receiver closely approximates the ideal rectangular step function shape desired whereby the signal to noise ratio is kept high. The receiver is particularly useful in mobile devices such as cell phones, tablet PC's and laptops.Type: ApplicationFiled: August 23, 2013Publication date: August 6, 2015Inventors: Harri Rapakko, Mikko Lintonen, Marko Pessa