Abstract: A method of forming a semiconductor package includes providing a lead frame including a metal frame at least partially surrounding a central opening and a plurality of tie bars connected between the metal frame and an adjacent stabilizing metal section, arranging the lead frame on a temporary carrier, arranging a semiconductor die on the temporary carrier within the central opening, forming a dielectric material that fills the central opening and encapsulates the semiconductor die, forming a first recess in the dielectric material above the semiconductor die so as to expose a first surface of the semiconductor die, electrically connecting terminals of the semiconductor die with the metal frame, and forming exposed outer contacts of the semiconductor package from the tie bars.

Abstract: A semiconductor chip package includes a semiconductor chip having a first side and a second side opposite the first side. The first side includes chip pads. The semiconductor chip package also includes a first leadframe structured to form a footprint of the semiconductor chip package. The semiconductor chip package further includes a structured metal plate disposed between the first leadframe and the semiconductor chip. The first side of the semiconductor chip faces the structured metal plate. A pattern of bond material is disposed between the first leadframe and the structured metal plate. The pattern of bond material is configured to electrically and mechanically connect structures of the first leadframe to structures of the structured metal plate. The semiconductor chip package also includes a mold compound embedding the first leadframe, the structured metal plate and the semiconductor chip.

Abstract: A method for fabricating one or more semiconductor packages includes: a substrate layer including one or more electrical contact regions; connecting a semiconductor die with one of the electrical contact regions; providing a heat dissipation member including one or more contact areas; attaching a tape to a backside of the heat dissipation member so that opposing ends of the tape extend beyond opposing side edges of the heat dissipation member; connecting a frontside of the heat dissipation member with the semiconductor die by coupling at least one contact area with the semiconductor die; placing a mold tool above the heat dissipation member and the substrate layer with the opposing ends of the tape extending out of the mold tool so that the tape is removable from outside the mold tool; filling an encapsulant into the mold cavity; and removing the tape.

Abstract: A electrical connection element includes a planar mating surface adapted for mating with a metal bonding surface, a rim that forms an enclosed shape around the planar mating surface, and a plurality of outgassing grooves formed in the planar mating surface, wherein each of the outgassing grooves comprises a proximal end that is spaced apart from the rim and a distal end that intersects the rim, and wherein a cross-sectional area of each of the outgassing grooves increases along a lengthwise direction going from the proximal end to the distal end.

Abstract: A transistor package includes a power transistor chip having first and second opposite sides. The first side has source, drain, and gate electrode metallizations. A multi-layer laminate substrate includes: a first structured metal layer facing the first side of the chip and electrically connected to the source electrode metallization, the drain electrode metallization, and the gate electrode metallization; a second structured metal layer having a source package terminal pad, a source sense package terminal pad, a drain package terminal pad, and a gate package terminal pad; at least one insulating layer between the structured metal layers; and vias running through the insulating layer and connecting segments of the first structured metal layer to the terminal pads of the second structured metal layer.

Abstract: A leadframe for flip chip attaching a semiconductor die thereon includes a rectangular area segmented into individual pads, the individual pads including a first pad, a second pad, and a third pad, wherein the first pad is larger than the second pad and larger than the third pad, and the second pad is located in a first corner area of the rectangular area and the third pad is located in a second corner area of the rectangular area, the second corner area being located diagonally opposite to the first corner area.

Abstract: An electronic device is disclosed. In one example, the electronic device comprises a carrier board, a metal inlay having a cavity and being arranged in the carrier board. At least one electronic component is arranged at least partially in the cavity and embedded in the carrier board. Electric contacts are located at a castellated edge of the carrier board.