Abstract: The present disclosure is directed to a plurality of waffle gate parallel transistors having a shared gate on a surface of a semiconductor substrate. The shared gate has connected channels that form a plurality of squares, lines of each of the squares over the perimeter of a respective source or drain region of the plurality of waffle gate parallel transistors. The shared gate includes squares of a first size and shape and a second size and shape. The squares having the first size and shape are each over a respective source region and the squares having the second size and shape are each over a respective drain region. Each of the squares having a first size and shape share at least one side with one of the squares having the second size and shape.

Abstract: The present disclosure is directed to a plurality of waffle gate parallel transistors having a shared gate on a surface of a semiconductor substrate. The shared gate has connected channels that form a plurality of squares, lines of each of the squares over the perimeter of a respective source or drain region of the plurality of waffle gate parallel transistors. The shared gate includes squares of a first size and shape and a second size and shape. The squares having the first size and shape are each over a respective source region and the squares having the second size and shape are each over a respective drain region. Each of the squares having a first size and shape share at least one side with one of the squares having the second size and shape.

Abstract: Integrated mask-programmable device, having a plurality of metal levels including a top metal level, a bottom metal level and a first intermediate metal level formed between the top and bottom metal levels, and a plurality of via levels arranged between the bottom and the first intermediate metal levels and between the first intermediate and the top metal levels and connecting each metal level to adjacent metal levels. The plurality of metal levels forms a first, a second and at least a third terminal, the top and bottom metal levels having at least two metal regions, and the first intermediate metal level having at least three metal regions. The first terminal is connected to third terminal or the second terminal is connected to the third terminal by modifying a single metal or via level.

Abstract: Integrated mask-programmable device, having a plurality of metal levels including a top metal level, a bottom metal level and a first intermediate metal level formed between the top and bottom metal levels, and a plurality of via levels arranged between the bottom and the first intermediate metal levels and between the first intermediate and the top metal levels and connecting each metal level to adjacent metal levels. The plurality of metal levels forms a first, a second and at least a third terminal, the top and bottom metal levels having at least two metal regions, and the first intermediate metal level having at least three metal regions. The first terminal is connected to third terminal or the second terminal is connected to the third terminal by modifying a single metal or via level.