Patents by Inventor Mildred S. Dresselhaus

Mildred S. Dresselhaus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9812525
    Abstract: A two-dimensional heterostructure is synthesized by producing a patterned first two-dimensional material on a growth substrate. The first two-dimensional material is patterned to define at least one void through which an exposed region of the growth substrate is exposed. Seed molecules are selectively deposited either on the exposed region of the growth substrate or on the patterned first two-dimensional material. A second two-dimensional material that is distinct from the first two-dimensional material is then grown from the deposited seed molecules.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: November 7, 2017
    Assignee: Massachusetts Institute of Technology
    Inventors: Mildred S. Dresselhaus, Jing Kong, Tomas A. Palacios, Xi Ling, Yuxuan Lin
  • Publication number: 20170170260
    Abstract: A two-dimensional heterostructure is synthesized by producing a patterned first two-dimensional material on a growth substrate. The first two-dimensional material is patterned to define at least one void through which an exposed region of the growth substrate is exposed. Seed molecules are selectively deposited either on the exposed region of the growth substrate or on the patterned first two-dimensional material. A second two-dimensional material that is distinct from the first two-dimensional material is then grown from the deposited seed molecules.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 15, 2017
    Applicant: Massachusetts Institute of Technology
    Inventors: Mildred S. Dresselhaus, Jing Kong, Tomas A. Palacios, Xi Ling, Yuxuan Lin
  • Publication number: 20150064471
    Abstract: A metal dichalcogenide layer is produced on a transfer substrate by seeding F16CuPc molecules on a surface of a growth substrate, growing a layer (e.g., a monolayer) of a metal dichalcogenide via chemical vapor deposition on the growth substrate surface seeded with F16CuPc molecules, and contacting the F16CuPc-molecule and metal-dichalcogenide coated growth substrate with a composition that releases the metal dichalcogenide from the growth substrate.
    Type: Application
    Filed: August 27, 2014
    Publication date: March 5, 2015
    Inventors: Mildred S. Dresselhaus, Jing Kong, Yi-Hsien Lee, Xi Ling
  • Publication number: 20140119981
    Abstract: A Bi1-xSbx thin film is provided that includes a Dirac-cone with different degrees of anisotropy in their electronic band structure by controlling the stoichiometry, film thickness, and growth orientation of the thin film, so as to result in a consistent inverse-effective mass tensor including non-parabolic or linear dispersion relations.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: Massachusetts Institute of Technology
    Inventors: Shuang Tang, Mildred S. Dresselhaus
  • Patent number: 8535553
    Abstract: A film of single-layer to few-layer graphene is formed by depositing a graphene film via chemical vapor deposition on a surface of a growth substrate. The surface on which the graphene is deposited can be a polycrystalline nickel film, which is deposited by evaporation on a SiO2/Si substrate. A protective support layer is then coated on the graphene film to provide support for the graphene film and to maintain its integrity when it is removed from the growth substrate. The surface of the growth substrate is then etched to release the graphene film and the protective support layer from the growth substrate, wherein the protective support layer maintains the integrity of the graphene film during and after its release from the growth substrate. After being released from the growth substrate, the graphene film and protective support layer can be applied onto an arbitrary target substrate for evaluation or use in any of a wide variety of applications.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: September 17, 2013
    Assignee: Massachusetts Institute of Technology
    Inventors: Jing Kong, Alfonso Reina Cecco, Mildred S. Dresselhaus
  • Patent number: 7875195
    Abstract: The presently disclosed invention provides for the fabrication of porous anodic alumina (PAA) films on a wide variety of substrates. The substrate comprises a wafer layer and may further include an adhesion layer deposited on the wafer layer. An anodic alumina template is formed on the substrate. When a rigid substrate such as Si is used, the resulting anodic alumina film is more tractable, easily grown on extensive areas in a uniform manner, and manipulated without danger of cracking. The substrate can be manipulated to obtain free-standing alumina templates of high optical quality and substantially flat surfaces. PAA films can also be grown this way on patterned and non-planar surfaces. Furthermore, under certain conditions, the resulting PAA is missing the barrier layer (partially or completely) and the bottom of the pores can be readily accessed electrically.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: January 25, 2011
    Assignee: Massachusetts Institute of Technology
    Inventors: Oded Rabin, Paul R. Herz, Mildred S. Dresselhaus, Akintunde I. Akinwande, Yu-Ming Lin
  • Publication number: 20100021708
    Abstract: A film of single-layer to few-layer graphene is formed by depositing a graphene film via chemical vapor deposition on a surface of a growth substrate. The surface on which the graphene is deposited can be a polycrystalline nickel film, which is deposited by evaporation on a SiO2/Si substrate. A protective support layer is then coated on the graphene film to provide support for the graphene film and to maintain its integrity when it is removed from the growth substrate. The surface of the growth substrate is then etched to release the graphene film and the protective support layer from the growth substrate, wherein the protective support layer maintains the integrity of the graphene film during and after its release from the growth substrate. After being released from the growth substrate, the graphene film and protective support layer can be applied onto an arbitrary target substrate for evaluation or use in any of a wide variety of applications.
    Type: Application
    Filed: April 13, 2009
    Publication date: January 28, 2010
    Applicant: Massachusetts Institute of Technology
    Inventors: Jing Kong, Alfonso Reina Cecco, Mildred S. Dresselhaus
  • Publication number: 20090226361
    Abstract: The nanoribbon structure includes a plurality of thin graphite ribbons having long and highly crystalline structure. A voltage is applied across the length of the thin graphite ribbons to cause current flow so as to increase crystallinity as well as establishing interplanar stacking order and well-defined graphene edges of the thin graphite ribbons.
    Type: Application
    Filed: March 5, 2008
    Publication date: September 10, 2009
    Inventors: Jessica Campos-Delgado, Mildred S. Dresselhaus, Morinobu Endo, Edgar E. Gracia-Espino, Xiaoting Jia, Jose Manuel Romo-Herrera, Humberto Terrones, Mauricio Terrones
  • Publication number: 20080210662
    Abstract: The presently disclosed invention provides for the fabrication of porous anodic alumina (PAA) films on a wide variety of substrates. The substrate comprises a wafer layer and may further include an adhesion layer deposited on the wafer layer. An anodic alumina template is formed on the substrate. When a rigid substrate such as Si is used, the resulting anodic alumina film is more tractable, easily grown on extensive areas in a uniform manner, and manipulated without danger of cracking. The substrate can be manipulated to obtain free-standing alumina templates of high optical quality and substantially flat surfaces. PAA films can also be grown this way on patterned and non-planar surfaces. Furthermore, under certain conditions the resulting PAA is missing the barrier layer (partially or completely) and the bottom of the pores can be readily accessed electrically.
    Type: Application
    Filed: August 1, 2007
    Publication date: September 4, 2008
    Inventors: Oded Rabin, Paul R. Herz, Mildred S. Dresselhaus, Akintunde I. Akinwande, Yu-Ming Lin
  • Patent number: 7267859
    Abstract: The presently disclosed invention provides for the fabrication of porous anodic alumina (PAA) films on a wide variety of substrates. The substrate comprises a wafer layer and may further include an adhesion layer deposited on the wafer layer. An anodic alumina template is formed on the substrate. When a rigid substrate such as Si is used, the resulting anodic alumina film is more tractable, easily grown on extensive areas in a uniform manner, and manipulated without danger of cracking. The substrate can be manipulated to obtain free-standing alumina templates of high optical quality and substantially flat surfaces PAA films can also be grown this way on patterned and non-planar surfaces. Furthermore, under certain conditions the resulting PAA is missing the barrier layer (partially or completely) and the bottom of the pores can be readily accessed electrically.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: September 11, 2007
    Assignee: Massachusetts Institute of Technology
    Inventors: Oded Rabin, Paul R. Herz, Mildred S. Dresselhaus, Akintunde I. Akinwande, Yu-Ming Lin
  • Patent number: 6627809
    Abstract: A carrier pocket engineering technique used to provide superlattice structures having relatively high values of the three-dimensional thermoelectric figure of merit (Z3DT) is described. Also described are several superlattice systems provided in acordance with the carrier pocket engineering technique. Superlattice structures designed in accordance with this technique include a plurality of alternating layers of at least two different semiconductor materials. First ones of the layers correspond to barrier layers and second ones of the layers correspond to well layers but barrier layers can also work as well layers for some certain carrier pockets and vice-versa. Each of the well layers are provided having quantum well states formed from carrier pockets at various high symmetry points in the Brillouin zone of the structure to provide the superlattice having a relatively high three-dimensional thermoelectric figure of merit.
    Type: Grant
    Filed: November 9, 2000
    Date of Patent: September 30, 2003
    Assignee: Massachusetts Institute of Technology
    Inventors: Takaaki Koga, Mildred S. Dresselhaus, Xiangzhong Sun, Steven B. Cronin
  • Patent number: 6452206
    Abstract: A superlattice structure for thermoelectric power generation includes m monolayers of a first barrier material alternating with n monolayers of a second quantum well material with a pair of monolayers defining a superlattice period and each of the materials having a relatively smooth interface therebetween. Each of the quantum well layers have a thickness which is less than the thickness of the barrier layer by an amount which causes substantial confinement of conduction carriers to the quantum well layer and the alternating layers provide a superlattice structure having a figure of merit which increases with increasing temperature.
    Type: Grant
    Filed: March 16, 1998
    Date of Patent: September 17, 2002
    Assignee: Massachusetts Institute of Technology
    Inventors: Theodore C. Harman, Mildred S. Dresselhaus, David L. Spears, Michael P. Walsh, Stephen B. Cronin, Xiangzhong Sun, Takaaki Koga
  • Patent number: 6359288
    Abstract: An array of nanowires having a relatively constant diameter and techniques and apparatus for fabrication thereof are described. In one embodiment, a technique for melting a material under vacuum and followed by pressure injection of the molten material into the pores of a porous substrate produces continuous nanowires. In another embodiment, a technique to systematically change the channel diameter and channel packing density of an anodic alumina substrate includes the steps of anodizing an aluminum substrate with an electrolyte to provide an anodic aluminum oxide film having a pore with a wall surface composition which is different than aluminum oxide and etching the pore wall surface with an acid to affect at least one of the surface properties of the pore wall and the pore wall composition.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: March 19, 2002
    Assignee: Massachusetts Institute of Technology
    Inventors: Jackie Y. Ying, Zhibo Zhang, Lei Zhang, Mildred S. Dresselhaus
  • Patent number: 6231744
    Abstract: An array of nanowires having a relativley constant diameter and techniques and apparatus for fabrication thereof are described. In one embodiment, a technique for melting a material under vacuum and followed by pressure injection of the molten material into the pores of a porous substrate produces continuous nanowires. In another embodiment, a technique to systematically change the channel diameter and channel packing density of an anodic alumina substrate includes the steps of anodizing an aluminum substrate with an electrolyte to provide an anodic aluminum oxide film having a pore with a wall surface composition which is different than aluminum oxide and etching the pore wall surface with an acid to affect at least one of the surface properties of the pore wall and the pore wall composition.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: May 15, 2001
    Assignee: Massachusetts Institute of Technology
    Inventors: Jackie Y. Ying, Zhibo Zhang, Lei Zhang, Mildred S. Dresselhaus
  • Patent number: 6060656
    Abstract: A superlattice structure for use in thermoelectric power generation systems includes m layers of a first one of Silicon and Antimony doped Silicon-Germanium alternating with n layers of Silicon-Germanium which provides a superlattice structure having a thermoelectric figure of merit which increases with increasing temperature above the maximum thermoelectric figure of merit achievable for bulk SiGe alloys.
    Type: Grant
    Filed: March 16, 1998
    Date of Patent: May 9, 2000
    Assignee: Regents of the University of California
    Inventors: Mildred S. Dresselhaus, Theodore C. Harman, Stephen B. Cronin, Takaaki Koga, Xiangzhong Sun, Kang L. Wang