Abstract: Platform controller, computer-readable storage media, and methods associated with initialization of a computing device. In embodiments, a platform controller may comprise a boot controller and one or more non-volatile memory modules, coupled with the boot controller. In embodiments, the one or more non-volatile memory modules may have first instructions and second instructions stored thereon. The first instructions may, when executed by a processor of a computing device hosting the platform controller, cause initialization of the computing device. The second instructions, when executed by the boot controller, may cause the boot controller to monitor at least a portion of the execution of the first instructions by the computing device and may generate a trace of the monitored portion of the execution of the first instructions. In embodiments, the trace may be stored in the one or more non-volatile memory modules. Other embodiments may be described and/or claimed.

Abstract: Platform controller, computer-readable storage media, and methods associated with initialization of a computing device. In embodiments, a platform controller may comprise a boot controller and one or more non-volatile memory modules, coupled with the boot controller. In embodiments, the one or more non-volatile memory modules may have first instructions and second instructions stored thereon. The first instructions may, when executed by a processor of a computing device hosting the platform controller, cause initialization of the computing device. The second instructions, when executed by the boot controller, may cause the boot controller to monitor at least a portion of the execution of the first instructions by the computing device and may generate a trace of the monitored portion of the execution of the first instructions. In embodiments, the trace may be stored in the one or more non-volatile memory modules. Other embodiments may be described and/or claimed.

Abstract: Techniques to buffer and present chunks are disclosed. In some embodiments, a first interface may receive chunks of a first cache line, and a second interface may receive chunks of a second cache line. A buffer may store chunks of the first cache line in a first chunk order and may store chunks of the second cache line in a second chunk order. A control unit may present a requester via the second interface with one or more chunks of the first cache line from the buffer.

Abstract: A device and method for servicing data requests from a processor or other input/output interface in a multi-processor environment by accessing a full or partial cache line of data. A system data chip is used to access the cache line of data using a bit pattern supplied by a system address chip. This access and transmission of data to the processor or the input/output interface is controlled by a control/status unit in the system data chip based on the value of control valid signals which include a first valid (DxV) signal and a second valid (CxV) signal. Also, data may be stored and retrieved in a first data format (linear chunk order) or a second data format (critical chunk order). When control by the control/status unit is based on the DxV signal value, a read of a data chunk may occur immediately after a write to temporary storage if the data is in the same chunk order and a merge or combination operation is not taking place.

Abstract: A device and method for servicing data requests from a processor or other input/output interface in a multi-processor environment by accessing a full or partial cache line of data. A system data chip is used to access the cache line of data using a bit pattern supplied by a system address chip. This access and transmission of data to the processor or the input/output interface is controlled by a control/status unit in the system data chip based on the value of control valid signals which include a first valid (DxV) signal and a second valid (CxV) signal. Also, data may be stored and retrieved in a first data format (linear chunk order) or a second data format (critical chunk order). When control by the control/status unit is based on the DxV signal value, a read of a data chunk may occur immediately after a write to temporary storage if the data is in the same chunk order and a merge or combination operation is not taking place.