Patents by Inventor Miles Lee

Miles Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for suppressing duplicative prefetches for branch target cache lines
    Patent number: 7461237
    Abstract: A system that suppresses duplicative prefetches for branch target cache lines. During operation, the system fetches a first cache line into in a fetch buffer. The system then prefetches a second cache line, which immediately follows the first cache line, into the fetch buffer. If a control transfer instruction in the first cache line has a target instruction which is located in the second cache line, the system determines if the control transfer instruction is also located at the end of the first cache line so that a corresponding delay slot for the control transfer instruction is located at the beginning of the second cache line. If so, the system suppresses a subsequent prefetch for a target cache line containing the target instruction because the target instruction is located in the second cache line which has already been prefetched.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: December 2, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Abid Ali, Paul Caprioli, Shailender Chaudhry, Miles Lee
  • Method and apparatus for suppressing duplicative prefetches for branch target cache lines
    Publication number: 20060242365
    Abstract: A system that suppresses duplicative prefetches for branch target cache lines. During operation, the system fetches a first cache line into in a fetch buffer. The system then prefetches a second cache line, which immediately follows the first cache line, into the fetch buffer. If a control transfer instruction in the first cache line has a target instruction which is located in the second cache line, the system determines if the control transfer instruction is also located at the end of the first cache line so that a corresponding delay slot for the control transfer instruction is located at the beginning of the second cache line. If so, the system suppresses a subsequent prefetch for a target cache line containing the target instruction because the target instruction is located in the second cache line which has already been prefetched.
    Type: Application
    Filed: April 20, 2005
    Publication date: October 26, 2006
    Inventors: Abid Ali, Paul Caprioli, Shailender Chaudhry, Miles Lee