Patents by Inventor Miles P. McGowan

Miles P. McGowan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for implementing an interface for I/O rings
    Patent number: 9135373
    Abstract: Disclosed are improved methods, systems, and computer program products for implementing an interface for visualizing, generating, and optimizing an I/O ring arrangement for an electronic design. A ribbon-based interface may be employed to visually see and control the design of the I/O ring.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: September 15, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Joseph P. Jarosz, Thaddeus C. McCracken, Miles P. McGowan
  • Method and system for optimizing placement of I/O element nodes of an I/O ring for an electronic design
    Patent number: 8683412
    Abstract: Disclosed are improved methods, systems, and computer program products for generating and optimizing an I/O ring arrangement for an electronic design. Corner packing is one approach that can be taken to optimizing an I/O ring. Stacking of I/O components provides another approach for optimizing an I/O ring.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: March 25, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Thaddeus Clay McCracken, Miles P. McGowan
  • Method and system for mapping memory when selecting an electronic product
    Patent number: 8516433
    Abstract: An improved approach is described for analyzing and estimating products having arrays of uncommitted logic, and matching these products to electronic designs. The approach can be applied to any type of product that include arrays of uncommitted logic, such as gate arrays and field programmable gate arrays. An approach is described for performing memory mapping in the context of selecting an electronic product having an array of uncommitted logic.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: August 20, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Thaddeus Clay McCracken, Miles P McGowan
  • Method and system for implementing a structure to implement I/O rings and die area estimations
    Patent number: 8443323
    Abstract: Disclosed are improved methods, systems, and computer program products for implementing an I/O ring structure to generate an I/O ring arrangement for an electronic design, and for performing chip planning and estimation based upon the I/O ring arrangement. Nodes in the I/O ring structure are used to track objects in the I/O ring.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: May 14, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Miles P. McGowan, Thaddeus Clay McCracken
  • Method and systems for implementing I/O rings and die area estimations
    Patent number: 8386981
    Abstract: Disclosed are improved methods, systems, and computer program products for generating an I/O ring arrangement for an electronic design, and for performing chip planning and estimation based upon the I/O ring arrangement.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: February 26, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Miles P. McGowan, Thaddeus Clay McCracken
  • Method and system for determining configurations
    Patent number: 8375344
    Abstract: An improved approach is described for analyzing and estimating products having arrays of uncommitted logic, and matching these products to electronic designs. The approach can be applied to any type of product that include arrays of uncommitted logic, such as gate arrays and field programmable gate arrays.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: February 12, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Miles P. McGowan, Thaddeus Clay McCracken, Joseph P. Jarosz, Jeffrey Kim Ng
  • METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND USER INTERFACE FOR PERFORMING POWER INFERENCE
    Publication number: 20100161303
    Abstract: An improved method, system, user interface, and computer program product is described for performing power-related inferences for an electronic design. According to some approaches, the electronic design is configured to include multiple power domains. Design information is used to infer the existence of power-management structures for and between the power domains in the electronic design. A graphical user interface is provided to visualize the inferred power-related structures and to allow the user to interact with and modify the design information related to power management.
    Type: Application
    Filed: December 22, 2008
    Publication date: June 24, 2010
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Miles P. McGowan, Joseph P. Jarosz, Thaddeus Clay McCracken