Patents by Inventor Miles Sanner

Miles Sanner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146272
    Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: Emre Ayranci, Miles Sanner
  • Publication number: 20240128945
    Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 18, 2024
    Inventors: Emre Ayranci, Miles Sanner, Ke Li, James Francis McElwee, Tero Tapio Ranta, Kevin Roberts, Chih-Chieh Cheng
  • Publication number: 20240113665
    Abstract: Methods and circuital arrangements for turning OFF branches of a multi-branch cascode amplifier are presented. First and second switching arrangements coupled to a branch allow turning OFF the branch while protecting transistors of the branch from a supply voltage that may be greater than a tolerable voltage of the transistors. The first switching arrangement includes a transistor-based switch that is in series connection with the transistors of the branch. The first switching arrangement drops the supply voltage during the OFF state of the branch and provides a conduction path for a current through the branch during the ON state of the branch. A resistor and a shunting switch are coupled to a gate of the transistor-based switch to reduce parasitic coupling effects of the transistor-based switch upon an RF signal coupled to the branch during the ON state and OFF state of the branch.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 4, 2024
    Inventors: Miles SANNER, Emre AYRANCI, Parvez DARUWALLA
  • Publication number: 20240039570
    Abstract: Methods and devices addressing design of wideband LNAs with gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed. The described methods and devices also address carrier aggregation requirements and provide solutions that can be used both in single-mode and split-mode operations.
    Type: Application
    Filed: August 7, 2023
    Publication date: February 1, 2024
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Patent number: 11881828
    Abstract: A multi-gain LNA with inductive source degeneration is presented. The inductive source degeneration is provided via a tunable degeneration network that includes an inductor in parallel with one or more switchable shunting networks. Each shunting network includes a shunting capacitor that can selectively be coupled in parallel to the inductor. A capacitance of the shunting capacitor is calculated so that a combined impedance of the inductor and the shunting capacitor at a narrowband frequency of operation is effectively an inductance. The inductance is calculated according to a desired gain of the LNA. According to one aspect, the switchable shunting network includes a resistor in series connection with the shunting capacitor to provide broadband frequency response stability of the tunable degeneration network. According to another aspect, the LNA includes a plurality of selectable branches to further control gain of the LNA.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: January 23, 2024
    Assignee: pSemi Corporation
    Inventors: Jing Li, Emre Ayranci, Miles Sanner
  • Publication number: 20240022220
    Abstract: A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the g m of the input stage of the amplifier, thus improving the noise figure of the amplifier.
    Type: Application
    Filed: July 13, 2023
    Publication date: January 18, 2024
    Inventors: Miles Sanner, Emre Ayranci
  • Patent number: 11870405
    Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: January 9, 2024
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner
  • Publication number: 20240007059
    Abstract: Circuits and methods for an LNA that enable selection of a first mode providing high gain with wide output impedance matching, and a second mode providing wideband output impedance matching with improved NF and linearity at moderate gain. Some embodiments allow multiple intermediate modes to enable selection of gain versus linearity and NF. One embodiment includes a matching network having an input terminal configured to be coupled to an amplified-signal terminal of an amplification core, and an output terminal, the matching network including a first inductor coupled between the input terminal and a first node; a second inductor coupled to the first node; a boosted amplification branch coupled between the input terminal and the output terminal; and a non-amplification branch coupled between the first node and the output terminal; wherein the boosted amplification branch is enabled in a first mode, and the non-amplification branch is enabled in a second mode.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Emre Ayranci, Jubaid Qayyum, Phanindra Yerramilli, Miles Sanner
  • Publication number: 20240007060
    Abstract: Circuits and methods for a radio frequency amplifier, such as an LNA, that include a wideband coupled input impedance matching network. One embodiment includes a first inductor coupled between a first terminal and a first node, the first terminal couplable to a degeneration terminal of an amplifier core; a second inductor coupled between a second terminal and either the first node or a second node, the second terminal couplable to an input terminal of the amplifier core; a third inductor coupled between the first node and a third terminal, the third terminal couplable to a reference potential; and, in a variant embodiment, a fourth inductor coupled between the second node and a fourth terminal, the fourth terminal couplable to the reference potential; wherein the first inductor and the second inductor are mutually coupled. Some embodiments allow multiple modes to allow tradeoffs of gain versus linearity and NF characteristics.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Emre Ayranci, Mengsheng Rui, Phanindra Yerramilli, Jubaid Qayyum, Vijay Katta, Miles Sanner
  • Publication number: 20240007058
    Abstract: Circuits and methods for an amplifier (particularly LNAs) that achieve wideband output impedance matching and high gain while simultaneously rejecting out-of-band (OOB) harmonic frequencies. Some embodiments allow multiple modes of operation to allow selection of gain versus linearity characteristics. One aspect of the present invention is improvement of the linearity and sensitivity of a whole RF “front end” (RFFE) receiver chain by suppressing OOB gain within an LNA component at higher order harmonic frequencies. Another aspect of the present invention are new wideband and ultra-wideband LNA load circuits that, while achieving high frequency OOB rejection, maintain in-band high gain and wideband output impedance matching at the same time. Yet another aspect of the present invention are new ultra-wideband LNA output impedance matching circuits.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Emre Ayranci, Mengsheng Rui, Miles Sanner, Steve Gao
  • Patent number: 11848648
    Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: December 19, 2023
    Assignee: pSemi Corporation
    Inventors: Kashish Pal, Emre Ayranci, Miles Sanner
  • Patent number: 11831280
    Abstract: Methods and circuital arrangements for turning OFF branches of a multi-branch cascode amplifier are presented. First and second switching arrangements coupled to a branch allow turning OFF the branch while protecting transistors of the branch from a supply voltage that may be greater than a tolerable voltage of the transistors. The first switching arrangement includes a transistor-based switch that is in series connection with the transistors of the branch. The first switching arrangement drops the supply voltage during the OFF state of the branch and provides a conduction path for a current through the branch during the ON state of the branch. A resistor and a shunting switch are coupled to a gate of the transistor-based switch to reduce parasitic coupling effects of the transistor-based switch upon an RF signal coupled to the branch during the ON state and OFF state of the branch.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: November 28, 2023
    Assignee: PSEMI CORPORATION
    Inventors: Miles Sanner, Emre Ayranci, Parvez Daruwalla
  • Patent number: 11804816
    Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: October 31, 2023
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner, Ke Li, James Francis McElwee, Tero Tapio Ranta, Kevin Roberts, Chih-Chieh Cheng
  • Publication number: 20230299727
    Abstract: A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.
    Type: Application
    Filed: March 20, 2023
    Publication date: September 21, 2023
    Inventors: Emre Ayranci, Miles Sanner
  • Patent number: 11728837
    Abstract: Methods and devices addressing design of wideband LNAs with gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed. The described methods and devices also address carrier aggregation requirements and provide solutions that can be used both in single-mode and split-mode operations.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: August 15, 2023
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Publication number: 20230253926
    Abstract: Methods and circuital arrangements for turning OFF branches of a multi-branch cascode amplifier are presented. First and second switching arrangements coupled to a branch allow turning OFF the branch while protecting transistors of the branch from a supply voltage that may be greater than a tolerable voltage of the transistors. The first switching arrangement includes a transistor-based switch that is in series connection with the transistors of the branch. The first switching arrangement drops the supply voltage during the OFF state of the branch and provides a conduction path for a current through the branch during the ON state of the branch. A resistor and a shunting switch are coupled to a gate of the transistor-based switch to reduce parasitic coupling effects of the transistor-based switch upon an RF signal coupled to the branch during the ON state and OFF state of the branch.
    Type: Application
    Filed: February 13, 2023
    Publication date: August 10, 2023
    Inventors: Miles SANNER, Emre AYRANCI, Parvez DARUWALLA
  • Patent number: 11705873
    Abstract: A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: July 18, 2023
    Assignee: pSemi Corporation
    Inventors: Miles Sanner, Emre Ayranci
  • Publication number: 20230147703
    Abstract: Methods and devices for realizing RF processing paths associated to different frequency bands are presented. According to one aspect, the RF processing paths are provided by a hybrid input LNA RF frontend that includes RF processing paths that are dedicated to specific frequency bands and RF processing paths that are shared between several frequency bands. Sharing of the RF processing paths is provided by an input combiner network and/or a multi-input cascode amplifier that includes a cascode transistor that is coupled to at least two input transistors. Further presented in a toolkit that includes circuit blocks that can be used in specific combinations to customize the RF processing paths to achieve specific performance or cost optimization. A decision tree based on performance and cost priorities assigned to each of the frequency bands is used to provide the specific combinations.
    Type: Application
    Filed: November 10, 2021
    Publication date: May 11, 2023
    Inventors: Emre AYRANCI, Miles SANNER
  • Publication number: 20230107218
    Abstract: A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.
    Type: Application
    Filed: October 13, 2022
    Publication date: April 6, 2023
    Inventors: Miles Sanner, Emre Ayranci
  • Patent number: 11611319
    Abstract: A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: March 21, 2023
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner