Abstract: For each predicted branch within a processor, an entry is maintained within a branch history table. The entry within the branch history table also includes an indication of the past record for that particular branch instruction, which indicates how correct the branch prediction has been in the past. When the field value associated with the predicted branch exceeds a certain threshold, indicating that the past predictions associated with that branch instruction have been at an unacceptable level, then the speculative branch instructions dispatching is suspended for that particular branch instruction. Alternative embodiments utilize a global indicator for suspending or cancelling instruction dispatch when the frequency of previous incorrect branch predictions increases beyond a preselected threshold.

Abstract: An apparatus for fetching data from a main memory into a primary cache memory of a processor. Instruction fetch requests are generated by the processor and assigned a priority level according to the predicted accuracy of the fetch request. The priority levels of different fetch requests are compared and the highest priority level fetch request is serviced first. An instruction cache line address N+1 is pre-fetched if there is a cache miss in the primary cache memory on address N+1.

Abstract: A method for selectively pre-fetching Line M+1 into an L1 instruction cache from an L2 cache or from main memory during the execution of Line M. If unresolved branches exist in pending Line M, Line M+1 is speculative and may be pre-fetched into L1 instruction cache only from L2 cache, not from main memory. Unresolved branches in pending Line M are resolved before Line M+1 is pre-fetched from main memory. If no unresolved branches exist, Line M is committed ("inevitable-speculative") and is pre-fetched from main memory. In this way, no potentially wasteful pre-fetches are performed and main memory bandwidth is preserved.