Patents by Inventor Milind Bhagavat
Milind Bhagavat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240063206Abstract: Systems, apparatuses, and methods for routing traffic through vertically stacked semiconductor dies are disclosed. A first semiconductor die has a second die stacked vertically on top of it in a three-dimensional integrated circuit. The first die includes a through silicon via (TSV) interconnect that does not traverse the first die. The first die includes one or more metal layers above the TSV, which connect to a bonding pad interface through a bonding pad via. If the signals transferred through the TSV of the first die are shared by the second die, then the second die includes a TSV aligned with the bonding pad interface of the first die. If these signals are not shared by the second die, then the second die includes an insulated portion of a wafer backside aligned with the bonding pad interface.Type: ApplicationFiled: October 30, 2023Publication date: February 22, 2024Inventors: John J. Wuu, Milind Bhagavat, Brett Wilkerson, Rahul Agarwal
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Patent number: 11495588Abstract: Various circuit boards with mounted passive components and method of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes at least partially encapsulating a first plurality of passive components in a molding material to create a first molded passive component group. The first molded passive component group is mounted on a surface of a circuit board. The first plurality of passive components are electrically connected to the circuit board.Type: GrantFiled: December 7, 2018Date of Patent: November 8, 2022Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Milind Bhagavat, Rahul Agarwal
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Patent number: 11011495Abstract: A data processor is implemented as an integrated circuit. The data processor includes a processor die. The processor die is connected to an integrated voltage regulator die using die-to-die bonding. The integrated voltage regulator die provides a regulated voltage to the processor die, and the processor die operates in response to the regulated voltage.Type: GrantFiled: August 23, 2018Date of Patent: May 18, 2021Assignee: Advanced Micro Devices, Inc.Inventors: Milind Bhagavat, David Hugh McIntyre, Rahul Agarwal
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Patent number: 10923430Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer and an interconnect chip at least partially encased in the first molding layer. The interconnect chip has a first side and a second side opposite the first side and a polymer layer on the first side. The polymer layer includes plural conductor traces. A redistribution layer (RDL) structure is positioned on the first molding layer and has plural conductor structures electrically connected to the plural conductor traces. The plural conductor traces provide lateral routing.Type: GrantFiled: June 30, 2019Date of Patent: February 16, 2021Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Chun-Hung Lin, Rahul Agarwal, Milind Bhagavat, Fei Guo
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Publication number: 20200411443Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer and an interconnect chip at least partially encased in the first molding layer. The interconnect chip has a first side and a second side opposite the first side and a polymer layer on the first side. The polymer layer includes plural conductor traces. A redistribution layer (RDL) structure is positioned on the first molding layer and has plural conductor structures electrically connected to the plural conductor traces. The plural conductor traces provide lateral routing.Type: ApplicationFiled: June 30, 2019Publication date: December 31, 2020Inventors: Fei Guo, Chun-Hung Lin, Rahul Agarwal, Milind Bhagavat
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Publication number: 20200185366Abstract: Various circuit boards with mounted passive components and method of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes at least partially encapsulating a first plurality of passive components in a molding material to create a first molded passive component group. The first molded passive component group is mounted on a surface of a circuit board. The first plurality of passive components are electrically connected to the circuit board.Type: ApplicationFiled: December 7, 2018Publication date: June 11, 2020Inventors: Milind Bhagavat, Rahul Agarwal
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Publication number: 20200066677Abstract: A data processor is implemented as an integrated circuit. The data processor includes a processor die. The processor die is connected to an integrated voltage regulator die using die-to-die bonding. The integrated voltage regulator die provides a regulated voltage to the processor die, and the processor die operates in response to the regulated voltage.Type: ApplicationFiled: August 23, 2018Publication date: February 27, 2020Applicant: Advanced Micro Devices, Inc.Inventors: Milind Bhagavat, David Hugh McIntyre, Rahul Agarwal
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Patent number: 10573630Abstract: A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.Type: GrantFiled: April 20, 2018Date of Patent: February 25, 2020Assignee: Advanced Micro Devices, Inc.Inventors: Brett P. Wilkerson, Milind Bhagavat, Rahul Agarwal, Dmitri Yudanov
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Publication number: 20190326272Abstract: A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.Type: ApplicationFiled: April 20, 2018Publication date: October 24, 2019Inventors: Brett P. Wilkerson, Milind Bhagavat, Rahul Agarwal, Dmitri Yudanov
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Patent number: 8593155Abstract: MEMS in-plane resonators include a substrate wafer, at least one resonant mass supported by the substrate wafer and configured to resonate substantially in-plane, and at least one transducer coupled to the at least one resonant mass for at least one of driving and sensing in-plane movement of the at least one resonant mass, wherein at least part of one surface of the resonant mass is configured for exposure to an external environment and wherein the at least one transducer is isolated from the external environment. Such MEMS in-plane resonators may be fabricated using conventional surface micromachining techniques and high-volume wafer fabrication processes and may be configured for liquid applications (e.g., viscometry, densitometry, chemical/biological sensing), gas sensing (e.g., where a polymer film is added to the sensor surface, further degrading the damping performance), or other applications.Type: GrantFiled: August 10, 2010Date of Patent: November 26, 2013Assignee: Analog Devices, Inc.Inventors: Andrew Sparks, Milind Bhagavat
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Publication number: 20120299868Abstract: A mutual capacitive touch panel providing improved noise immunity and improved spatial resolution is described. The touch panel includes a drive line having a plurality of drive electrodes. The touch panel further includes a sense line arranged at an angle with respect to the drive line and the sense line having a plurality of sense electrodes, such that each of the plurality of sense electrodes overlies one of the plurality of drive electrodes. The touch panel is further configured such that a perimeter of each of the plurality of drive electrodes encompasses a perimeter of at least one of the plurality of sense electrodes.Type: ApplicationFiled: December 20, 2011Publication date: November 29, 2012Applicant: BROADCOM CORPORATIONInventors: Milind Bhagavat, David Sobel, John Walley, Sumant Ranganathan
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Publication number: 20120112765Abstract: MEMS in-plane resonators include a substrate wafer, at least one resonant mass supported by the substrate wafer and configured to resonate substantially in-plane, and at least one transducer coupled to the at least one resonant mass for at least one of driving and sensing in-plane movement of the at least one resonant mass, wherein at least part of one surface of the resonant mass is configured for exposure to an external environment and wherein the at least one transducer is isolated from the external environment. Such MEMS in-plane resonators may be fabricated using conventional surface micromachining techniques and high-volume wafer fabrication processes and may be configured for liquid applications (e.g., viscometry, densitometry, chemical/biological sensing), gas sensing (e.g., where a polymer film is added to the sensor surface, further degrading the damping performance), or other applications.Type: ApplicationFiled: August 10, 2010Publication date: May 10, 2012Applicant: ANALOG DEVICES, INC.Inventors: Andrew Sparks, Milind Bhagavat
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Patent number: 8058144Abstract: A method for capping a MEMS wafer to form a hermetically sealed device. The method includes applying a glass bonding agent to the cap wafer and burning off organic material in the glass bonding agent. The cap wafer/glass bonding agent combination is then cleaned to reduce lead in the combination. The cleaning is preferably accomplished using an oxygen plasma. The MEMS device is coated with a WASA agent. The cap wafer is then bonded to the MEMS wafer by heating this combination in a capping gas atmosphere of hydrogen molecules in a gas such as nitrogen, argon or neon. This method of capping the MEMS wafer can reduce stiction in the MEMS device.Type: GrantFiled: May 19, 2009Date of Patent: November 15, 2011Assignee: Analog Devices, Inc.Inventors: Milind Bhagavat, Erik Tarvin, Firas Sammoura, Kuang Yang, Andrew Sparks
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Patent number: 7981723Abstract: A capped wafer includes a device wafer and an opposing cap wafer with an annular glass frit disposed between the device wafer and the cap wafer. The glass frit and the opposing wafers define a sealed volume that encloses the capped devices, and the glass frit may support the wafer cap during removal of excess wafer cap material from the capped wafer. A method of fabricating a capped wafer includes fabricating an annular intermediate layer between a device wafer and a cap wafer. In an alternate embodiment, a plurality of unsingulated dice each contains bond pads along a single edge and are arranged on a device wafer in an alternating order so that the bond pads of a first die are adjacent to the bond pads of a second die.Type: GrantFiled: November 11, 2008Date of Patent: July 19, 2011Assignee: Analog Devices, Inc.Inventors: Xue'en Yang, Milind Bhagavat, Erik Tarvin
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Publication number: 20100117221Abstract: A capped wafer includes a device wafer and an opposing cap wafer with an annular glass frit disposed between the device wafer and the cap wafer. The glass frit and the opposing wafers define a sealed volume that encloses the capped devices, and the glass frit may support the wafer cap during removal of excess wafer cap material from the capped wafer. A method of fabricating a capped wafer includes fabricating an annular intermediate layer between a device wafer and a cap wafer. In an alternate embodiment, a plurality of unsingulated dice each contains bond pads along a single edge and are arranged on a device wafer in an alternating order so that the bond pads of a first die are adjacent to the bond pads of a second die.Type: ApplicationFiled: November 11, 2008Publication date: May 13, 2010Applicant: ANALOG DEVICES, INC.Inventors: Xue'en Yang, Milind Bhagavat, Erik Tarvin
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Publication number: 20090294879Abstract: A method for capping a MEMS wafer to form a hermetically sealed device. The method includes applying a glass bonding agent to the cap wafer and burning off organic material in the glass bonding agent. The cap wafer/glass bonding agent combination is then cleaned to reduce lead in the combination. The cleaning is preferably accomplished using an oxygen plasma. The MEMS device is coated with a WASA agent. The cap wafer is then bonded to the MEMS wafer by heating this combination in a capping gas atmosphere of hydrogen molecules in a gas such as nitrogen, argon or neon. This method of capping the MEMS wafer can reduce stiction in the MEMS device.Type: ApplicationFiled: May 19, 2009Publication date: December 3, 2009Applicant: ANALOG DEVICES, INC.Inventors: Milind Bhagavat, Erik Tarvin, Firas Sammoura, Kuang Yang, Andrew Sparks
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Publication number: 20080020684Abstract: A hydrostatic pad for use in holding a semiconductor wafer during grinding of the wafer by grinding wheels. The pad includes hydrostatic pockets formed in a face of the body directly opposed to the wafer The pockets are adapted for receiving fluid through the body and into the pockets to provide a barrier between the body face and the workpiece while still applying pressure to hold the workpiece during grinding. The hydrostatic pads allow the wafer to rotate relative to the pads about their common axis. The pockets are oriented to reduce hydrostatic bending moments that are produced in the wafer when the grinding wheels shift or tilt relative to the hydrostatic pads, helping prevent nanotopology degradation of surfaces of the wafer commonly caused by shift and tilt of the grinding wheels.Type: ApplicationFiled: January 20, 2005Publication date: January 24, 2008Applicant: MEMC ELECTRONIC MATERIALS, INCORPORATEDInventors: Milind Bhagavat, Puneet Gupta, Roland Vandamme, Takuto Kazama, Noriyuki Tachi
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Publication number: 20070179659Abstract: A double side grinder comprises a pair of grinding wheels and a pair of hydrostatic pads operable to hold a flat workpiece (e.g., semiconductor wafer) so that part of the workpiece is positioned between the grinding wheels and part of the workpiece is positioned between the hydrostatic pads. At least one sensor measures a distance between the workpiece and the respective sensor for assessing nanotopology of the workpiece. In a method of the invention, a distance to the workpiece is measured during grinding and used to assess nanotopology of the workpiece. For instance, a finite element structural analysis of the workpiece can be performed using sensor data to derive at least one boundary condition. The nanotopology assessment can begin before the workpiece is removed from the grinder, providing rapid nanotopology feedback. A spatial filter can be used to predict the likely nanotopology of the workpiece after further processing.Type: ApplicationFiled: December 28, 2006Publication date: August 2, 2007Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Roland Vandamme, Milind Bhagavat
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Publication number: 20070179660Abstract: A double side grinder comprises a pair of grinding wheels and a pair of hydrostatic pads operable to hold a flat workpiece (e.g., semiconductor wafer) so that part of the workpiece is positioned between the grinding wheels and part of the workpiece is positioned between the hydrostatic pads. At least one sensor measures a distance between the workpiece and the respective sensor for assessing nanotopology of the workpiece. In a method of the invention, a distance to the workpiece is measured during grinding and used to assess nanotopology of the workpiece. For instance, a finite element structural analysis of the workpiece can be performed using sensor data to derive at least one boundary condition. The nanotopology assessment can begin before the workpiece is removed from the grinder, providing rapid nanotopology feedback. A spatial filter can be used to predict the likely nanotopology of the workpiece after further processing.Type: ApplicationFiled: December 28, 2006Publication date: August 2, 2007Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Sumeet Bhagavat, Milind Bhagavat, Roland Vandamme, Tomomi Komura