Abstract: A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the step of depositing a dielectric layer over a reflectance stop layer. The reflectance stop layer is disposed above a component that is disposed on a semiconductor wafer. During a determination of the thickness of the dielectric layer using a reflected signal of light, the reflectance stop layer substantially reduces any light from reflecting off of the component. Therefore, the present invention provides a method and system that provides more accurate endpoint detection during a CMP process of semiconductor wafers. As a result of the present invention, an operator of a CMP machine knows precisely when to stop a CMP process of a semiconductor wafer.

Abstract: A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the step of depositing a dielectric layer over a reflectance stop layer. The reflectance stop layer is disposed above a component that is disposed on a semiconductor wafer. During a determination of the thickness of the dielectric layer using a reflected signal of light, the reflectance stop layer substantially reduces any light from reflecting off of the component. Therefore, the present invention provides a method and system that provides more accurate endpoint detection during a CMP process of semiconductor wafers. As a result of the present invention, an operator of a CMP machine knows precisely when to stop a CMP process of a semiconductor wafer.

Abstract: A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the step of depositing a dielectric layer over a reflectance stop layer. The reflectance stop layer is disposed above a component that is disposed on a semiconductor wafer. During a determination of the thickness of the dielectric layer using a reflected signal of light, the reflectance stop layer substantially reduces any light from reflecting off of the component. Therefore, the present invention provides a method and system that provides more accurate endpoint detection during a CMP process of semiconductor wafers. As a result of the present invention, an operator of a CMP machine knows precisely when to stop a CMP process of a semiconductor wafer.

Abstract: A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas. Specifically, one embodiment of the present invention utilizes a dry abrasive polishing pad to abrade the desired surface of the semiconductor wafer within a vacuum planarization chamber. As a result of abrading the surface, the abrasive polishing pad breaks the chemical bonds of a thin layer of the dielectric surface material.

Abstract: A method for fabricating inter-metal oxide in semiconductor devices and semiconductor devices is provided. The method begins by providing a semiconductor substrate having a plurality of patterned conductive features. The method then moves to where a high density plasma (HDP) operation is performed and is configured to deposit an oxide layer over the plurality of patterned conductive features. The HDP operation includes a deposition component and a sputtering component. The deposition component is driven by a deposition gas and the sputtering component is driven by a sputtering gas. The HDP operation forms oxide pyramids over the plurality of patterned conductive features. The method now moves to where the deposition gas is removed to close off the deposition component in the HDP operation. Now, the HDP operation is run with the sputtering gas while retaining the sputtering component.

Abstract: A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas.

Abstract: A method for fabricating inter-metal oxide in semiconductor devices and semiconductor devices is provided. The method begins by providing a semiconductor substrate having a plurality of patterned conductive features. The method then moves to where a high density plasma (HDP) operation is performed and is configured to deposit an oxide layer over the plurality of patterned conductive features. The HDP operation includes a deposition component and a sputtering component. The deposition component is driven by a deposition gas and the sputtering component is driven by a sputtering gas. The HDP operation forms oxide pyramids over the plurality of patterned conductive features. The method now moves to where the deposition gas is removed to close off the deposition component in the HDP operation. Now, the HDP operation is run with the sputtering gas while retaining the sputtering component.

Abstract: A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the step of depositing a dielectric layer over a reflectance stop layer. The reflectance stop layer is disposed above a component that is disposed on a semiconductor wafer. During a determination of the thickness of the dielectric layer using a reflected signal of light, the reflectance stop layer substantially reduces any light from reflecting off of the component. Therefore, the present invention provides a method and system that provides more accurate endpoint detection during a CMP process of semiconductor wafers. As a result of the present invention, an operator of a CMP machine knows precisely when to stop a CMP process of a semiconductor wafer.

Abstract: A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas. Specifically, one embodiment of the present invention utilizes a dry abrasive polishing pad to abrade the desired surface of the semiconductor wafer within a vacuum planarization chamber. As a result of abrading the surface, the abrasive polishing pad breaks the chemical bonds of a thin layer of the dielectric surface material.

Abstract: A method of forming sharp oxide peaks on the surface of a semiconductor wafer for the purpose of conditioning polishing pads used during a Chemical Mechanical Polishing process is disclosed. In order to create oxide peaks on the surface of a wafer, additional elements are added to a trace layer of the wafer. An oxide layer is deposited over the additional elements using an Electron Cyclotron Resonance Chemical Vapor Deposition process, which includes a sputtering step, in order to create sharp peaks in the oxide layer over the additional lines. In some embodiments, the additional elements may be formed from a multiplicity of rectangular blocks over which pyramid-like oxide peaks are created. In others, they may be formed from a multiplicity of rectangular blocks connected by narrow lines over which pyramid-like oxide peaks and knife-edged peaks, respectively, are created.

Abstract: A method of commonizing the pattern density of topography for different layers of semiconductor wafers to improve the Chemical Mechanical Polishing process used during wafer processing is disclosed. In order to achieve a predetermined pattern density of topography on the surface of a wafer, dummy raised lines are inserted as necessary into gaps between active conductive traces on a trace layer. In some embodiments, the predetermined pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised lines are formed from a metallic material that is deposited in one single step with an insulating layer deposited over both the active conductive traces and the dummy raised lines prior to the Chemical Mechanical Polishing process. In other applications, the dummy raised lines are formed from the insulating layer.

Abstract: A method of improving the planarity of spin-on-glass layers in semiconductor wafer processing is disclosed. Gaps in between active conductive traces in a trace layer that exceed a predetermined distance are provided with dummy lines having a specific geometry in order to improve the planarity achieved in subsequently applied spin-on glass layers. In some embodiments, the predetermined distance is greater than approximately 1 micrometer, as for example in the range of approximately 3 to 6 micrometers. In some applications, both the active conductive traces and the dummy lines are formed from a metallic material that is deposited in one single step with a passivation layer being deposited over both the conductive traces and the raised lines prior to application of the spin-on glass layer.

Abstract: A method of forming sharp oxide peaks on the surface of a semiconductor wafer for the purpose of conditioning polishing pads used during a Chemical Mechanical Polishing process is disclosed. In order to create oxide peaks on the surface of a wafer, additional elements are added to a trace layer of the wafer. An oxide layer is deposited over the additional elements using an Electron Cyclotron Resonance Chemical Vapor Deposition process, which includes a sputtering step, in order to create sharp peaks in the oxide layer over the additional lines. In some embodiments, the additional elements may be formed from a multiplicity of rectangular blocks over which pyramid-like oxide peaks are created. In others, they may be formed from a multiplicity of rectangular blocks connected by narrow lines over which pyramid-like oxide peaks and knife-edged peaks, respectively, are created.

Abstract: A chemical mechanical polishing system for processing semiconductor wafers has a polishing arm and carrier assembly that press the topside surface of a semiconductor wafer against a motor driven, rotating polishing pad. Improved uniformity of material removal, as well as improved stability of material removal rate, is achieved through the use of a controller that applies a variable wafer backside pressure to the wafers being polished. More specifically, a control subsystem maintains a wafer count, corresponding to how many wafers have been polished by the polishing pad. The control subsystem regulates the backside pressure applied to each wafer in accordance with a predetermined function such that the backside pressure increases monotonically as the wafer count increases. In the preferred embodiment, the control system regulates the backside pressure in accordance with a linear function of the form: Backside Pressure=A+(B.times.Wafer Count).

Abstract: A method of commonizing the pattern density of topography for different layers of semiconductor wafers to improve the Chemical Mechanical Polishing process used during wafer processing is disclosed. In order to achieve a predetermined pattern density of topography on the surface of a wafer, dummy raised lines are inserted as necessary into gaps between active conductive traces on a trace layer. In some embodiments, the predetermined pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised lines are formed from a metallic material that is deposited in one single step with an insulating layer deposited over both the active conductive traces and the dummy raised lines prior to the Chemical Mechanical Polishing process. In other applications, the dummy raised lines are formed from the insulating layer.

Abstract: Spin-on glass etchback is a technique commonly used to planarize the surface of a semiconductor wafer during fabrication. The etch rate of spin-on glass is largely affected by the amount of oxide exposed during the spin-on glass etchback process. The amount of oxide exposed during spin-on glass etchback is dependent upon the underlying pattern density of topography. A method of standardizing the pattern density of topography for different layers of semiconductor wafers to improve the spin-on glass etchback process used to planarize the surface of a wafer during processing is disclosed. In order to achieve a standardized pattern density of topography on the surface of a wafer, dummy raised areas are added into gaps between active conductive traces on a trace layer. In some embodiments, the standardized pattern density is in the range of approximately 40% to 80%.

Abstract: A method of manufacturing a microscope probe tip comprises the steps of depositing a first material over a substrate, such as silicon oxide over a silicon substrate using chemical vapor deposition. The first material is patterned to define at least one structural protrusion. During this patterning, the first material is etched back. Then a second material, such as silicon oxide, is deposited over the protrusion using an electron cyclotron resonance (ECR) process, which grows a sloped surface to form the microscope probe tip. In another aspect of the invention, two different resolution Atomic Force Microscope (AFM) probe tips are grown. Then, the cantilevers are coupled together to provide an AFM with two probe tips having different resolutions.

Abstract: An integrated circuit fabrication method begins with semiconductor devices formed on a substrate. A patterned metal layer is deposited on the substrate to connect the semiconductor devices. A nitride layer is deposited over the metal layer and substrate. The nitride layer topography comprises hills located over metal regions and valleys located over non-metal regions. Spin-on-glass (SOG) is deposited over the nitride layer, thereby filling the valleys and covering the hills. The SOG layer and the nitride layer hills are etched back at substantially the same etch rate, using plasma etching, to form a planar surface. An oxide layer is then deposited over the planar surface to encapsulate the semiconductor devices, metal layer, nitride layer and SOG layer. Vias may then be etched through the oxide layer and the nitride layer to expose portions of the underlying metal layer and facilitate upper layer metal connections thereto.