Abstract: Data is received that is derived from each of a plurality of inspection camera modules forming part of a quality assurance inspection system. The data includes a feed of images of a plurality of objects passing in front of the respective inspection camera module. Thereafter, the received data is separately analyzed by each inspection camera module using at least one image analysis inspection tool. The results of the analyzing can be correlated for each inspection camera module on an object-by-object basis. The correlating can use timestamps for the images and/or detected unique identifiers within the images and can be performed by a cloud-based server and/or a local edge computer. Access to the correlated results can be provided to a consuming application or process.

Abstract: Data is received that includes a feed of images of a plurality of objects passing in front of each of a plurality of inspection camera modules forming part of each of a plurality of stations. The stations can together form part of a quality assurance inspection system. The objects when combined or assembled, can form a product. The received data derived from each inspection camera module can be separately analyzed using at least one image analysis inspection tool. The analyzing can include visually detecting a unique identifier for each object. The images are transmitted with results from the inspection camera modules along with the unique identifiers to a cloud-based server to correlate results from the analyzing for each inspection camera module on an product-by-product basis. Access to the correlated results can be provided to a consuming application or process via the cloud-based server.

Abstract: Data is received that is derived from each of a plurality of inspection camera modules forming part of a quality assurance inspection system. The data includes a feed of images of a plurality of objects passing in front of the respective inspection camera module. Thereafter, the received data is separately analyzed by each inspection camera module using at least one image analysis inspection tool. The results of the analyzing can be correlated for each inspection camera module on an object-by-object basis. The correlating can use timestamps for the images and/or detected unique identifiers within the images and can be performed by a cloud-based server and/or a local edge computer. Access to the correlated results can be provided to a consuming application or process.

Abstract: A multiprocessor computing system includes a serial bus and implements a boot protocol in which each processor compares a vector field of a boot message issued on the serial bus by a first processor with an ID of the processor; a match indicating that the first processor is a bootstrap processor (BSP). The non-BSPs are halted and, after issuing a final message on the bus, the BSP fetches code to start a reset sequence. The BSP then sends a message to wake the non-BSPs, after which time the operating system software is given control. Faulty processors that fail to participate in the boot protocol do not stop the selection of a BSP as long as one processor in the system is functional.

Abstract: A method and apparatus for providing an interface from a processor to a bus. The interface is capable of operating at a speed selected from a plurality of speeds. An execution unit is coupled to a register file. The register file comprises a plurality of registers. Each of the registers of the register file is for storing data. The execution unit is for executing instructions. An instruction cache is coupled to the execution unit. The instruction cache and ROM is for storing instructions that can be used by the execution unit. A reset means is also coupled to the execution unit. Furthermore, a bus speed indication means is coupled to the execution unit and to the register files. The bus speed indication means is for receiving a bus speed indication signal. The bus speed indication signal is for indicating the selected operating speed for the bus interface. The reset signal is provided to the reset means and the bus speed indication signal is provided to the bus speed indication means.

Abstract: An apparatus for generating a pulse clock signal for a multiple-stage synchronizer provides a pulse clock signal to a synchronizer. The synchronizer synchronizes data received in a first clock domain, which is referenced to a first clock signal, to a second clock domain, which is referenced to a second clock signal. The apparatus includes a synchronization pulse generator and a multiplexer. The synchronization pulse generator generates a synchronization pulse based on the first clock signal and the second clock signal. The multiplexer outputs one of either the first clock signal or the synchronization pulse as the pulse clock signal based on an input control signal.

Abstract: In a microprocessor, an apparatus and method for performing memory functions and issuing bus cycles. Special microinstructions are stored in microcode ROM. These microinstructions are used to perform the memory functions and to generate the special bus cycles. Initially, an address corresponding to a requested operation to be performed is generated for one of these special microinstructions. That special microinstruction, along with its address, is then transmitted over the bus to the various units of the microprocessor. When each of the units receives the microinstruction, it determines whether that microinstruction is to be ignored based on the address. If a particular unit ignores the microinstruction, the microinstruction is forwarded to subsequent units in the pipeline for processing. Otherwise, if that particular unit performs the requested operation as specified by the microinstruction's address.

Abstract: A multi-processor system that supports multiple programmable interrupt controllers (PIC). An advanced programmable interrupt controller (APIC) provides interface between the processors and the PICs. The APIC provides interface between processors and other I/O devices also. The APIC sends an interrupt request data packet with a first field set to a processor identification number, a second field set to a type of the device that sent interrupt request and a third field. The third field is set to an interrupt vector if the device sending the interrupt request to the APIC is a device other than PIC. The third field is set to a predetermined identification number of the PIC if the interrupt request is from the PIC. A processor, to which the interrupt is directed to, receives the packet. If the interrupt request is from a PIC, the processor uses the third field to identify which of the multiple PICs caused the interrupt.

Abstract: A cache control method and mechanism for an external cache memory having multiple cache lines using interagent communications to cause invalidating the external cache memory, flushing the external cache memory and/or changing the coherency state of lines in the external cache memory.