Patents by Inventor Milind Manohar Kulkarni
Milind Manohar Kulkarni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8386684Abstract: A data processing system is provided which comprises at least two processing units (100, 101, 102) each for executing a plurality of tasks and an interrupt handling unit (200) for receiving an interrupt to be processed by the data processing system and for distributing the interrupt to one of the at least two processing units (100, 101, 102). The processing unit (100, 101, 102) to which the interrupt is distributed stops its current execution of the task and processes the interrupt. The interrupt handling unit (200) is adapted to determine whether the processing units (100, 101, 102) are executing a critical section (CS) of the task. The interrupt handling unit (200) distributes the interrupt to one of the processing units (100, 101, 102), which is not executing a critical section (CS) of a task.Type: GrantFiled: December 8, 2008Date of Patent: February 26, 2013Assignee: NXP B.V.Inventors: Ranjith Gopalakrishnan, Milind Manohar Kulkarni
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Patent number: 8041869Abstract: A method and system for bus arbitration to be used in a system having a plurality of data handling units (110a, . . . , 110d) and a shared bus (140) with a plurality of data-lines. The invention provides a method and an system to carry out the method, having steps of; receiving data transfer requests from the data handling units; selecting a set of data transfer requests the allowance of which serves a maximum number of data handling units and utilizes a maximum number of data-lines, and; allowing the data handling units that issued said selected set of data transfer requests to access said bus in a single bus cycle.Type: GrantFiled: June 17, 2010Date of Patent: October 18, 2011Assignee: Koninklijke Philips Electronics N.V.Inventors: Bijo Thomas, Milind Manohar Kulkarni
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Publication number: 20110113215Abstract: The present invention proposes a method and a system for dynamic cache partitioning for application tasks in a multiprocessor. An approach for dynamically resizing cache partitions based on the execution phase of the application tasks is provided. The execution phases of the application tasks are identified and updated in a tabular form. Cache partitions are resized during a particular instance of the execution of application tasks such that the necessary and sufficient amount of cache space is allocated to the application tasks at any given point of time. The cache partition size is determined according to the working set requirement of the tasks during its execution, which is monitored dynamically or statically. Cache partitions are resized according to the execution phase of the task dynamically such that unnecessary reservation of the entire cache is avoided and hence an effective utilization of the cache is achieved.Type: ApplicationFiled: February 24, 2007Publication date: May 12, 2011Applicant: NXP B.V.Inventors: Bijo Thomas, Sriram Krishnan, Milind Manohar Kulkarni, Sainath Karlapalem
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Publication number: 20110106995Abstract: A data processing system is provided which comprises at least two processing units (100, 101, 102) each for executing a plurality of tasks and an interrupt handling unit (200) for receiving an interrupt to be processed by the data processing system and for distributing the interrupt to one of the at least two processing units (100, 101, 102). The processing unit (100, 101, 102) to which the interrupt is distributed stops its current execution of the task and processes the interrupt. The interrupt handling unit (200) is adapted to determine whether the processing units (100, 101, 102) are executing a critical section (CS) of the task. The interrupt handling unit (200) distributes the interrupt to one of the processing units (100, 101, 102), which is not executing a critical section (CS) of a task.Type: ApplicationFiled: December 8, 2008Publication date: May 5, 2011Applicant: NXP B.V.Inventors: Ranjith Gopalakrishnan, Milind Manohar Kulkarni
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Patent number: 7899966Abstract: A method for distributing interrupt load to processors in a multiprocessor system. The method includes executing current transactions with multiple processors (104, 106, 108) where each transaction is associated with one of the processors, generating an interrupt request, estimating a transaction completion time for each processor and directing the interrupt request (102) to the processor having the least estimated transaction completion time. Estimating a transaction completion time occurs periodically so that information pertaining to transaction times is stored and continually updated. According to one aspect of the invention, the step of estimating a transaction completion time for each processor occurs when the interrupt request is generated. According to another aspect of the invention, the step of communicating the interrupt request includes communicating the interrupt request to an intermediary processor prior to estimating the transaction completion time.Type: GrantFiled: January 4, 2007Date of Patent: March 1, 2011Assignee: NXP B.V.Inventor: Milind Manohar Kulkarni
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Publication number: 20100257296Abstract: A method and system for bus arbitration to be used in a system having a plurality of data handling units (110a, . . . , 110d) and a shared bus (140) with a plurality of data-lines. The invention provides a method and an system to carry out the method, having steps of; receiving data transfer requests from the data handling units; selecting a set of data transfer requests the allowance of which serves a maximum number of data handling units and utilizes a maximum number of data-lines, and; allowing the data handling units that issued said selected set of data transfer requests to access said bus in a single bus cycle.Type: ApplicationFiled: June 17, 2010Publication date: October 7, 2010Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Bijo Thomas, Milind Manohar Kulkarni
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Patent number: 7765350Abstract: A method and system for bus arbitration to be used in a system having a plurality of data handling units (110a, . . . , 110d) and a shared bus (140) with a plurality of data-lines. The invention provides a method and an system to carry out the method, having steps of; receiving data transfer requests from the data handling units; selecting a set of data transfer requests the allowance of which serves a maximum number of data handling units and utilizes a maximum number of data-lines, and; allowing the data handling units that issued said selected set of data transfer requests to access said bus in a single bus cycle.Type: GrantFiled: September 7, 2006Date of Patent: July 27, 2010Assignee: Koninklijke Philips Electronics N.V.Inventors: Bijo Thomas, Milind Manohar Kulkarni
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Patent number: 7698514Abstract: A data processing system includes processing units for processing data, at least one memory for storing data from the processing units, an interconnect for connecting the processing units and the memory. The processing units request write access to the memory via the interconnect to write data into the memory. At least one arbiter performs interconnect arbitration for the access to the memory from the processing units, wherein interconnect arbitration is performed based on the minimum logic level changes of the interconnect as introduced by the write accesses of the processing units to the memory. If more than one write request is available from different processing units the interconnect arbitration (interconnect access), is granted to that processing unit, whose data to be sent to the memory via the interconnect results in minimum logic level changes to the interconnect. Power dissipation due to switching of logic levels is reduced.Type: GrantFiled: June 14, 2005Date of Patent: April 13, 2010Assignee: NXP B.V.Inventors: Milind Manohar Kulkarni, Bijo Thomas
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Publication number: 20090228625Abstract: A method for distributing interrupt load to processors in a multiprocessor system. The method includes executing current transactions with multiple processors (104, 106, 108) where each transaction is associated with one of the processors, generating an interrupt request, estimating a transaction completion time for each processor and directing the interrupt request (102) to the processor having the least estimated transaction completion time. Estimating a transaction completion time occurs periodically so that information pertaining to transaction times is stored and continually updated. According to one aspect of the invention, the step of estimating a transaction completion time for each processor occurs when the interrupt request is generated. According to another aspect of the invention, the step of communicating the interrupt request includes communicating the interrupt request to an intermediary processor prior to estimating the transaction completion time.Type: ApplicationFiled: January 4, 2007Publication date: September 10, 2009Applicant: NXP B.V.Inventor: Milind Manohar Kulkarni
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Publication number: 20090177842Abstract: A data processing system for processing at least one application is provided. The data processing system comprises a processor (100) for executing the application. The system furthermore comprises a cache memory (200) being associated to the processor (100) for caching data and/or instructions for the processor (100). The system furthermore comprises a memory unit (400) for storing data and/or instructions for the application. The memory unit (400) comprises a plurality of memory partitions (401-404). Data with similar data attributes are stored in the same memory partition (401-404). A predefined prefetching pattern is associated to each of the memory partitions (401-404).Type: ApplicationFiled: February 26, 2007Publication date: July 9, 2009Applicant: NXP B.V.Inventor: Milind Manohar Kulkarni
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Publication number: 20090172226Abstract: A data processing system comprising a plurality of processing units (Dv1-DvM) for processing data, at least one memory means (MM) for storing data from said plurality of processing units (Dv1-DvM), an interconnect means (IM) for connecting said plurality of processing units (Dv1-DvM) and said at least one memory means (MM) is provided. Said processing units (Dv1-DvM) are adapted to request a write access to said at least one memory means (MM) via the interconnect means (IM) in order to write data into said at least one memory means (MM). At least one arbiter means (AU) is provided for performing an interconnect arbitration for the access to said at least one memory means (MM) from said plurality of processing units (Dv1-DvM), wherein said interconnect arbitration is performed based on the minimum logic level changes of said interconnect means (IM) as introduced by the write accesses of said plurality of processing units (Dv1-DvM) to said at least one memory means (MM).Type: ApplicationFiled: June 14, 2005Publication date: July 2, 2009Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Milind Manohar Kulkarni, Bijo Thomas
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Patent number: 7480756Abstract: An electronic data processing circuit contains a plurality of data handling units (10a-d, 16a-b) with data outputs, at least part of the data handling units having address outputs. The data handling units supply words of preferably selectable size to a bus. A bus controller (20) is arranged to control access to the bus in successive access cycles. The bus controller (20) causes data bits from a plurality of data words from respective ones of the data handling units (10a-d, 16a-b), to be placed in combination on the data lines in a same bus cycle. The bus controller causes write addresses that the respective ones of the data handling units (10a-d, 16a-b) supply for respective ones of the plurality of data words to be placed on the address lines in a plurality of respective bus cycles. Preferably, the temporal or spatial arrangement of the data words on the bus lines adapted so as to minimize the number of logic level changes on the bus.Type: GrantFiled: November 3, 2004Date of Patent: January 20, 2009Assignee: Koninklijke Philips Electronics N.V.Inventors: Milind Manohar Kulkarni, Bijo Thomas
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Publication number: 20080312718Abstract: A skin stimulation device is provided with a stimulator (4) for locally stimulating skin at a skin location on a body part, for applying acupressure for example. The device has a storage unit (42) that stores location information specifying the skin location relative to a feature of the body part. The device contains a camera (2) for capturing image data of the skin. A processing circuit (40) processes the captured image data to determine a position of said feature and to identify the skin location based on the location information and the determined position of the feature. The device then preferably indicates whether the stimulator is at a stimulation location and/or automatically starts stimulation.Type: ApplicationFiled: December 7, 2006Publication date: December 18, 2008Applicant: Koninklijke Philips Electronics, N.V.Inventors: Milind Manohar Kulkarni, Ramzan Nadaf, Sala Lakshmanan, Jagadeesh Chandra Bose Rantham Prabhakara
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Publication number: 20080313482Abstract: The present invention comprises a plurality of memory banks (102, 103) with independent power controls (110) such that any memory banks (102, 103) not actively engaged in storing partitioned data can be powered down by dynamic voltage scaling. A memory management unit (112) is used to re-map partitions so they occupy fewer banks of memory, and a re-partition processor (102) is used to compute how partitions can be packed and squeezed together to use fewer banks of memory. Overall system power dissipation is therefore reduced by limiting the number of memory banks (102, 103) being powered up.Type: ApplicationFiled: December 20, 2006Publication date: December 18, 2008Applicant: NXP B.V.Inventors: Sainath Karlapalem, Milind Manohar Kulkarni
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Publication number: 20080276045Abstract: The apparatus of the present invention improves performance of computing systems by enabling a multi-core or multi-processor system to deterministically identify cache memory (100) blocks that are ripe for victimization and also prevent victimization of memory blocks that will be needed in the immediate future. To achieve these goals, the system has a FIFO with schedule information available in the form of Estimated Production Time (EPT) (102) and Estimated Consumption Time (ECT) (104) counters to make suitable pre-fetch and write-back decisions so that data transmission is overlapped with processor execution.Type: ApplicationFiled: December 21, 2006Publication date: November 6, 2008Applicant: NXP B.V.Inventors: Milind Manohar Kulkarni, Narendranath Udupa
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Publication number: 20080256278Abstract: A method and system for bus arbitration to be used in a system having a plurality of data handling units (110a, . . . 110d) and a shared bus (140) with a plurality of data-lines. The invention provides a method and an system to carry out the method, having steps of; receiving data transfer requests from the data handling units; selecting a set of data transfer requests the allowance of which serves a maximum number of data handling units and utilizes a maximum number of data-lines, and; allowing the data handling units that issued said selected set of data transfer requests to access said bus in a single bus cycle.Type: ApplicationFiled: September 7, 2006Publication date: October 16, 2008Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.Inventors: Bijo Thomas, Milind Manohar Kulkarni