Patents by Inventor Milind P. Shah
Milind P. Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9269681Abstract: Some implementations provide a semiconductor device that includes a substrate coupled to a die through a thermal compression bonding process. The semiconductor device also includes a trace coupled to the substrate. The trace includes a first conductive material having a first oxidation property. The trace also includes a first surface layer including a second conductive material having a second oxidation property. The second oxidation property is less susceptible to oxidation than the first oxidation property. The first and second conductive materials are configured to provide an electrical path between the die and the substrate. The first surface layer has a thickness that is 0.3 microns (?m) or less.Type: GrantFiled: January 15, 2013Date of Patent: February 23, 2016Assignee: QUALCOMM IncorporatedInventors: Houssam W. Jomaa, Omar J. Bchir, Milind P. Shah, Manuel Aldrete, Chin-Kwan Kim
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Patent number: 9131634Abstract: A radio frequency package on package (PoP) circuit is described. The radio frequency package on package (PoP) circuit includes a first radio frequency package. The first radio frequency package includes radio frequency components. The radio frequency package on package (PoP) circuit also includes a second radio frequency package. The second radio frequency package includes radio frequency components. The first radio frequency package and the second radio frequency package are in a vertical configuration. The radio frequency components on the first radio frequency package are designed to reduce the effects of ground inductance.Type: GrantFiled: November 14, 2012Date of Patent: September 8, 2015Assignee: QUALCOMM IncorporatedInventors: Aristotele Hadjichristos, Gurkanwal Singh Sahota, Steven C Ciccarelli, David J Wilding, Ryan D Lane, Christian Holenstein, Milind P Shah
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Patent number: 8847375Abstract: An integrated circuit package includes a microelectromechanical systems (MEMS) device embedded in a packaging substrate. The MEMS device is located on a die embedded in the packaging substrate and covered by a hermetic seal. Low-stress material in the packaging substrate surrounds the MEMS device. Additionally, interconnects may be used as standoffs to reduce stress on the MEMS device. The MEMS device is embedded a distance into the packaging substrate leaving for example, 30-80 microns, between the hermetic seal of the MEMS device and the support surface of the packaging substrate. Embedding the MEMS device results in lower stress on the MEMS device.Type: GrantFiled: January 28, 2010Date of Patent: September 30, 2014Assignee: QUALCOMM IncorporatedInventors: Milind P. Shah, Mario Francisco Velez, Fifin Sweeney
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Patent number: 8802556Abstract: Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized.Type: GrantFiled: February 20, 2013Date of Patent: August 12, 2014Assignee: QUALCOMM IncorporatedInventors: Omar J. Bchir, Milind P. Shah, Houssam W. Jomaa, Manuel Aldrete, Chin-Kwan Kim
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Publication number: 20140175658Abstract: Sonic implementations pertain to a semiconductor device that includes a packaging substrate, a trace coupled to the packaging substrate, and a solder resist layer that covers part of the trace. The trace includes a first portion having a first width, and a second portion having a second width that is wider than the first width. In some implementations, the second portion having the second width increases the area of the trace coupled to the packaging substrate to reduce the likelihood of the trace peeling from the packaging substrate. In some implementations, the solder resist layer further includes an opening such that the second portion of the trace is exposed. In some implementations, the trace further includes a third portion located between the first portion and second portion of the trace and wherein the third portion of the trace is exposed through an opening in the solder resist layer.Type: ApplicationFiled: February 12, 2013Publication date: June 26, 2014Applicant: Qualcomm IncorporatedInventors: Chin-Kwan Kim, Houssam W. Jomaa, Milind P. Shah, Manuel Aldrete, Omar J. Bchir
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Publication number: 20140159238Abstract: Some exemplary implementations of this disclosure pertain to an integrated circuit package that includes a substrate, a first die and a second die. The substrate includes a first set of traces and a second set of traces. The first set of traces has a first pitch. The second set of traces has a second pitch. The first pitch is less than the second pitch. In some implementations, a pitch of a set of traces defines a center to center distance between two neighboring traces, or bonding pads on a substrate. The first die is coupled to the substrate by a thermal compression bonding process. In some implementations, the first die is coupled to the first set of traces of the substrate. The second die is coupled to the substrate by a reflow bonding process. In some implementations, the second die is coupled to the second set of traces of the substrate.Type: ApplicationFiled: December 7, 2012Publication date: June 12, 2014Applicant: QUALCOMM IncorporatedInventors: Manuel Aldrete, Milind P. Shah, Omar J. Bchir, Houssam W. Jomaa, Chin-Kwan Kim
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Patent number: 8742603Abstract: A backside mold configuration (BSMC) process for manufacturing packaged integrated circuits includes applying a mold compound to a side of a packaging substrate opposite an attached die. The mold compound is deposited on a dielectric (such as photo resist). The mold compound and dielectric are patterned after coupling a die to the packaging substrate to expose a contact pad of the packaging substrate. After patterning the mold compound and dielectric, a packaging connection is coupled to contact pads through the mold compound and dielectric. The mold compound surrounding the packaging connection reduces warpage of the packaging substrate during processing. Additionally, patterning the dielectric after attaching the die improves reliability of the packaging connection.Type: GrantFiled: September 15, 2010Date of Patent: June 3, 2014Assignee: QUALCOMM IncorporatedInventors: Omar J. Bchir, Milind P. Shah, Sashidhar Movva
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Publication number: 20140138831Abstract: Some implementations provide a semiconductor device that includes a substrate coupled to a die through a thermal compression bonding process. The semiconductor device also includes a trace coupled to the substrate. The trace includes a first conductive material having a first oxidation property. The trace also includes a first surface layer including a second conductive material having a second oxidation property. The second oxidation property is less susceptible to oxidation than the first oxidation property. The first and second conductive materials are configured to provide an electrical path between the die and the substrate. The first surface layer has a thickness that is 0.3 microns (?m) or less.Type: ApplicationFiled: January 15, 2013Publication date: May 22, 2014Applicant: QUALCOMM IncorporatedInventors: Houssam W. Jomaa, Omar J. Bchir, Milind P. Shah, Manuel Aldrete, Chin-Kwan Kim
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Publication number: 20140131857Abstract: Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized.Type: ApplicationFiled: February 20, 2013Publication date: May 15, 2014Applicant: Qualcomm IncorporatedInventors: Omar J. Bchir, Milind P. Shah, Houssam W. Jomaa, Manuel Aldrete, Chin-Kwan Kim
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Patent number: 8703602Abstract: Conventional metallization processes fail at high density or small feature size patterns. For example, during patterning dry films may collapse or lift-off resulting in short circuits or open circuits in the metallization pattern. An exemplary method for metallization of integrated circuits includes forming features such as trenches, pads, and planes in a dielectric layer and depositing and selectively treating a seed layer in desired features of the dielectric layer. The treated regions of the seed layer may be used as a seed for electroless deposition of conductive material, such as copper, into the features. When the seed layer is a catalytic ink, the seed layer may be treated by curing the catalytic ink with a laser.Type: GrantFiled: December 2, 2010Date of Patent: April 22, 2014Assignee: QUALCOMM IncorporatedInventors: Omar J. Bchir, Milind P. Shah, Sashidhar Movva
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Patent number: 8633597Abstract: In a multi-module integrated circuit package having a package substrate and package contacts, a die is embedded in the package substrate with thermal vias that couple hotspots on the embedded die to some of the package contacts.Type: GrantFiled: March 1, 2010Date of Patent: January 21, 2014Assignee: QUALCOMM IncorporatedInventors: Fifin Sweeney, Milind P. Shah, Mario Francisco Velez, Damion B. Gastelum
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Publication number: 20120139112Abstract: Conventional metallization processes fail at high density or small feature size patterns. For example, during patterning dry films may collapse or lift-off resulting in short circuits or open circuits in the metallization pattern. An exemplary method for metallization of integrated circuits includes forming features such as trenches, pads, and planes in a dielectric layer and depositing and selectively treating a seed layer in desired features of the dielectric layer. The treated regions of the seed layer may be used as a seed for electroless deposition of conductive material, such as copper, into the features. When the seed layer is a catalytic ink, the seed layer may be treated by curing the catalytic ink with a laser.Type: ApplicationFiled: December 2, 2010Publication date: June 7, 2012Applicant: QUALCOMM IncorporatedInventors: Omar J. Bchir, Milind P. Shah, Sashidhar Movva
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Publication number: 20120090883Abstract: A package substrate includes conductive layers and a dielectric interposed between the conductive layers. The dielectric includes a stiffening material component and a neat resin doped with a negative coefficient of thermal expansion (CTE) fiber.Type: ApplicationFiled: July 15, 2011Publication date: April 19, 2012Applicant: QUALCOMM INCORPORATEDInventors: Omar J. Bchir, Milind P. Shah, Sashidhar Movva
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Publication number: 20120080787Abstract: An electrical package and a method of forming the electrical package, where the electrical package has a substrate with a frontside, an intergrated circuit coupled to the frontside of the substrate, and at least one non-collapsible metal connector created on the frontside of the first substrate.Type: ApplicationFiled: August 30, 2011Publication date: April 5, 2012Applicant: QUALCOMM INCORPORATEDInventors: Milind P. Shah, Omar J. Bchir, Sashidhar Movva
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Patent number: 8093982Abstract: An inductor or transformer for use in integrated circuit devices that includes a high-resistivity substrate. The inductor includes a plurality of conductive traces around the substrate forming a continuous conductive path from a first to a second port. The conductive path can be solenoid-shaped. Some of the conductive traces can be formed during back-end-of-line processing or backside plating of an integrated circuit die. The transformer includes a first inductor with input and output ports, and a first continuous conductive path therebetween; and a second inductor with input and output ports, and a second continuous conductive path therebetween. The second inductor is independent of and electromagnetically coupled to the first inductor. The first and second conductive paths can be solenoid-shaped. The first conductive path can be interleaved with the second conductive path.Type: GrantFiled: March 25, 2010Date of Patent: January 10, 2012Assignee: QUALCOMM IncorporatedInventors: Jonghae Kim, Milind P. Shah, Chi Shun Lo, Je-Hsiung Lan, Xia Li, Matthew Michael Nowak
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Publication number: 20110285026Abstract: A backside mold configuration (BSMC) process for manufacturing packaged integrated circuits includes applying a mold compound to a side of a packaging substrate opposite an attached die. The mold compound is deposited on a dielectric (such as photo resist). The mold compound and dielectric are patterned after coupling a die to the packaging substrate to expose a contact pad of the packaging substrate. After patterning the mold compound and dielectric, a packaging connection is coupled to contact pads through the mold compound and dielectric. The mold compound surrounding the packaging connection reduces warpage of the packaging substrate during processing. Additionally, patterning the dielectric after attaching the die improves reliability of the packaging connection.Type: ApplicationFiled: September 15, 2010Publication date: November 24, 2011Applicant: QUALCOMM IncorporatedInventors: Omar J. Bchir, Milind P. Shah, Sashidhar Movva
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Publication number: 20110234357Abstract: An inductor or transformer for use in integrated circuit devices that includes a high-resistivity substrate. The inductor includes a plurality of conductive traces around the substrate forming a continuous conductive path from a first to a second port. The conductive path can be solenoid-shaped. Some of the conductive traces can be formed during back-end-of-line processing or backside plating of an integrated circuit die. The transformer includes a first inductor with input and output ports, and a first continuous conductive path therebetween; and a second inductor with input and output ports, and a second continuous conductive path therebetween. The second inductor is independent of and electromagnetically coupled to the first inductor. The first and second conductive paths can be solenoid-shaped. The first conductive path can be interleaved with the second conductive path.Type: ApplicationFiled: March 25, 2010Publication date: September 29, 2011Applicant: QUALCOMM INCORPORATEDInventors: Jonghae Kim, Milind P. Shah, Chi Shun Lo, Je-Hsiung Lan, Xia Li, Matthew Michael Nowak
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Publication number: 20110210438Abstract: In a multi-module integrated circuit package having a package substrate and package contacts, a die is embedded in the package substrate with thermal vias that couple hotspots on the embedded die to some of the package contacts.Type: ApplicationFiled: March 1, 2010Publication date: September 1, 2011Applicant: QUALCOMM IncorporatedInventors: Fifin Sweeney, Milind P. Shah, Mario Francisco Velez, Damion B. Gastelum
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Publication number: 20110180926Abstract: An integrated circuit package includes a microelectromechanical systems (MEMS) device embedded in a packaging substrate. The MEMS device is located on a die embedded in the packaging substrate and covered by a hermetic seal. Low-stress material in the packaging substrate surrounds the MEMS device. Additionally, interconnects may be used as standoffs to reduce stress on the MEMS device. The MEMS device is embedded a distance into the packaging substrate leaving for example, 30-80 microns, between the hermetic seal of the MEMS device and the support surface of the packaging substrate. Embedding the MEMS device results in lower stress on the MEMS device.Type: ApplicationFiled: January 28, 2010Publication date: July 28, 2011Applicant: QUALCOMM INCORPORATEDInventors: Milind P. Shah, Mario Francisco Velez, Fifin Sweeney