Abstract: In one embodiment, a test system comprises: a test partition configured to perform test operations; a centralized test controller for controlling testing by the test partition; and a test link interface controller configured to communicate between the centralized test controller and the test partition, wherein the test link interface controller controls dynamic changes to external pads associated with the test operations. The test link interface controller dynamically selects between an input direction and output direction for the external pads. The test link interface includes a pin direction controller that generates direction control signals based on the state of local test controller and communicates the desired direction to a boundary scan cell associated with the pin. The boundary scan cell programs the pad to either input or output direction depending on direction control signals. The input direction corresponds to driving test data and the output direction corresponds to observing test data.

Abstract: A method for performing scan based tests is presented. The method comprises routing scan data serially from a plurality of I/O ports to a plurality of partitions of an integrated circuit using a first clock signal operating at a first frequency, where each partition comprises a plurality of internal scan chains. The method also comprises deserializing the scan data to feed internal scan chains. Further, the method comprises generating a plurality of second clock signals operating at a second frequency using the first clock signal, where each partition receives a respective one of the plurality of second clock signals and where the plurality of second clock signals are staggered where each pulses at a different time. Finally, the method comprises shifting in the scan data into the internal scan chains at the rate of the second frequency.

Abstract: A method for reducing peak power during a scan shift cycle is presented. The method comprises multiplexing a test clock with a functional clock on a integrated circuit at the root of a clock tree. The method also comprises adding a plurality of delay elements on a clock path, wherein the clock path is a signal resulting from the multiplexing. Further, the method comprises routing the clock path to a plurality of cores and a cache, e.g., an L2C cache, on the integrated circuit. Finally the method comprises staggering the test clock received by each of the plurality of cores and the cache by employing the delay elements during a scan shift cycle.

Abstract: A method for testing an integrated circuit to reduce peak power problems during scan capture mode is presented. The method comprises programming a respective duration of a first time window for each of a plurality of cores and a cache on the integrated circuit. It further comprises counting the number of pulses of a first clock signal during the first time window for each of the plurality of cores and the cache. Subsequently, the method comprises staggering capture pulses to the plurality of cores and the cache by generating pulses of a second clock signal for each of the plurality of cores and the cache during a respective second time window, wherein the number of pulses generated is based on the respective number of first clock signal pulses counted for each of the plurality of cores and the cache.

Abstract: Efficient scan system presented can comprise: an array including a plurality of array non scannable components and a plurality of array quasi-scannable components wherein each column of the array includes at least one of the plurality of array quasi-scannable components; and an input interface configured to receive and selectively forward data and scan information to at least a portion of the array. At least a portion of the plurality of array quasi-scannable components can form a diagonal pattern in the array. The input interface can include: an input interface selection component wherein an output of the input interface selection component is communicatively coupled to an input of the input interface quasi-scannable component associated with one row and an input of the input interface selection component is communicatively coupled to an output of one of the plurality of array quasi-scannable components associated with another row.

Abstract: A method for testing an integrated circuit to reduce peak power problems during scan capture mode is presented. The method comprises programming a respective duration of a first time window for each of a plurality of cores and a cache on the integrated circuit. It further comprises counting the number of pulses of a first clock signal during the first time window for each of the plurality of cores and the cache. Subsequently, the method comprises staggering capture pulses to the plurality of cores and the cache by generating pulses of a second clock signal for each of the plurality of cores and the cache during a respective second time window, wherein the number of pulses generated is based on the respective number of first clock signal pulses counted for each of the plurality of cores and the cache.

Abstract: A method for performing scan based tests is presented. The method comprises routing scan data serially from a plurality of I/O ports to a plurality of partitions of an integrated circuit using a first clock signal operating at a first frequency, wherein each partition comprises a plurality of internal scan chains. The method also comprises deserializing the scan data to feed internal scan chains. Further, the method comprises generating a plurality of second clock signals operating at a second frequency using the first clock signal, wherein each partition receives a respective one of the plurality of second clock signals and wherein the plurality of second clock signals are staggered wherein each pulses at a different time. Finally, the method comprises shifting in the scan data into the internal scan chains at the rate of the second frequency.

Abstract: A method for reducing peak power during a scan shift cycle is presented. The method comprises multiplexing a test clock with a functional clock on a integrated circuit at the root of a clock tree. The method also comprises adding a plurality of delay elements on a clock path, wherein the clock path is a signal resulting from the multiplexing. Further, the method comprises routing the clock path to a plurality of cores and a cache, e.g., an L2C cache, on the integrated circuit. Finally the method comprises staggering the test clock received by each of the plurality of cores and the cache by employing the delay elements during a scan shift cycle.

Abstract: An apparatus includes a register of an integrated circuit for shifting a scan test pattern in response to a scan enable signal. The register includes: a shift input for receiving the scan test pattern; a system logic input for receiving a system logic signal; a clock input for receiving a next clock pulse; a scan enable input for switching the register between a shift mode and a normal mode; a register output for latching the shift input in the shift mode or the system logic input in the normal mode in response to the next clock pulse; and a scan enable gating circuit coupled to the scan enable input for holding the register in the shift mode while the scan enable signal is in the shift mode and immediately following a transition of the scan enable signal from the shift mode to the normal mode until after the register output has latched the shift input in response to the next clock pulse following the transition of the scan enable signal to the normal mode.

Abstract: An apparatus includes a register of an integrated circuit for shifting a scan test pattern in response to a scan enable signal. The register includes: a shift input for receiving the scan test pattern; a system logic input for receiving a system logic signal; a clock input for receiving a next clock pulse; a scan enable input for switching the register between a shift mode and a normal mode; a register output for latching the shift input in the shift mode or the system logic input in the normal mode in response to the next clock pulse; and a scan enable gating circuit coupled to the scan enable input for holding the register in the shift mode while the scan enable signal is in the shift mode and immediately following a transition of the scan enable signal from the shift mode to the normal mode until after the register output has latched the shift input in response to the next clock pulse following the transition of the scan enable signal to the normal mode.