Patents by Inventor Milko Paolucci
Milko Paolucci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9974187Abstract: Representative implementations of devices and techniques provide off-board power conversion. A power cable is arranged to distribute power from a power supply to a peripheral component. An active circuit is integrated into the cable, converting the power en route from the power supply to the peripheral component.Type: GrantFiled: April 22, 2013Date of Patent: May 15, 2018Assignee: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Martin Standing, Andrew Roberts, Milko Paolucci
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Patent number: 9559047Abstract: Representative implementations of devices and techniques provide improved thermal performance of a chip die disposed within a layered printed circuit board (PCB). Passive components may be strategically located on one or more surfaces of the PCB. The passive components may be arranged to conduct heat generated by the chip die away from the chip die.Type: GrantFiled: October 18, 2012Date of Patent: January 31, 2017Assignee: Infineon Technologies Austria AGInventors: Martin Standing, Milko Paolucci
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Patent number: 9530773Abstract: Embodiments relate to bootstrap circuits integrated with at least one other device, such as a power transistor or other semiconductor device. In embodiments, the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap diode, or the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap transistor. The bootstrap capacitor comprises a semiconductor-based capacitor, as opposed to an electrolytic, ceramic or other capacitor, in embodiments. The integration of the bootstrap circuit with another circuit or device, such as a power transistor device in one embodiment, is at a silicon-level in embodiments, rather than as a module-like system-in-package of conventional approaches. In other words, the combination of the bootstrap circuit elements and power transistor or other device forms a system-on-silicon, or an integrated circuit, in embodiments, and additionally can be arranged in a single package.Type: GrantFiled: October 20, 2015Date of Patent: December 27, 2016Assignee: Infineon Technologies Austria AGInventors: Martin Vielemeyer, Sylvain Leomant, Milko Paolucci, Martin Poelzl
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Patent number: 9443798Abstract: Representative implementations of devices and techniques provide improved thermal performance of a chip die disposed within a layered printed circuit board (PCB). Passive components may be strategically located on one or more surfaces of the PCB. The passive components may be arranged to conduct heat generated by the chip die away from the chip die.Type: GrantFiled: October 18, 2012Date of Patent: September 13, 2016Assignee: Infineon Technologies Austria AGInventors: Martin Standing, Milko Paolucci
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Publication number: 20160043072Abstract: Embodiments relate to bootstrap circuits integrated with at least one other device, such as a power transistor or other semiconductor device. In embodiments, the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap diode, or the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap transistor. The bootstrap capacitor comprises a semiconductor-based capacitor, as opposed to an electrolytic, ceramic or other capacitor, in embodiments. The integration of the bootstrap circuit with another circuit or device, such as a power transistor device in one embodiment, is at a silicon-level in embodiments, rather than as a module-like system-in-package of conventional approaches. In other words, the combination of the bootstrap circuit elements and power transistor or other device forms a system-on-silicon, or an integrated circuit, in embodiments, and additionally can be arranged in a single package.Type: ApplicationFiled: October 20, 2015Publication date: February 11, 2016Inventors: Martin Vielemeyer, Sylvain Leomant, Milko Paolucci, Martin Poelzl
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Patent number: 9171738Abstract: Embodiments relate to bootstrap circuits integrated with at least one other device, such as a power transistor or other semiconductor device. In embodiments, the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap diode, or the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap transistor. The bootstrap capacitor comprises a semiconductor-based capacitor, as opposed to an electrolytic, ceramic or other capacitor, in embodiments. The integration of the bootstrap circuit with another circuit or device, such as a power transistor device in one embodiment, is at a silicon-level in embodiments, rather than as a module-like system-in-package of conventional approaches. In other words, the combination of the bootstrap circuit elements and power transistor or other device forms a system-on-silicon, or an integrated circuit, in embodiments, and additionally can be arranged in a single package.Type: GrantFiled: December 18, 2012Date of Patent: October 27, 2015Assignee: Infineon Technologies Austria AGInventors: Martin Vielemeyer, Sylvain Leomant, Milko Paolucci, Martin Poelzl
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Patent number: 8946767Abstract: A semiconductor device and method are disclosed. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side. Contact areas of the first n-type channel FET and the second n-type channel FET are electrically separated from each other.Type: GrantFiled: June 4, 2012Date of Patent: February 3, 2015Assignee: Infineon Technologies Austria AGInventors: Oliver Haeberlen, Walter Rieger, Martin Vielemeyer, Lutz Goergens, Martin Poelzl, Milko Paolucci, Johannes Schoiswohl, Sonja Krumrey
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Publication number: 20140311794Abstract: Representative implementations of devices and techniques provide off-board power conversion. A power cable is arranged to distribute power from a power supply to a peripheral component. An active circuit is integrated into the cable, converting the power en route from the power supply to the peripheral component.Type: ApplicationFiled: April 22, 2013Publication date: October 23, 2014Inventors: Martin STANDING, Andrew ROBERTS, Milko PAOLUCCI
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Publication number: 20140167069Abstract: Embodiments relate to bootstrap circuits integrated with at least one other device, such as a power transistor or other semiconductor device. In embodiments, the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap diode, or the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap transistor. The bootstrap capacitor comprises a semiconductor-based capacitor, as opposed to an electrolytic, ceramic or other capacitor, in embodiments. The integration of the bootstrap circuit with another circuit or device, such as a power transistor device in one embodiment, is at a silicon-level in embodiments, rather than as a module-like system-in-package of conventional approaches. In other words, the combination of the bootstrap circuit elements and power transistor or other device forms a system-on-silicon, or an integrated circuit, in embodiments, and additionally can be arranged in a single package.Type: ApplicationFiled: December 18, 2012Publication date: June 19, 2014Inventors: Martin Vielemeyer, Sylvain Leomant, Milko Paolucci, Martin Poelzl
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Publication number: 20140110820Abstract: Representative implementations of devices and techniques provide improved thermal performance of a chip die disposed within a layered printed circuit board (PCB). Passive components may be strategically located on one or more surfaces of the PCB. The passive components may be arranged to conduct heat generated by the chip die away from the chip die.Type: ApplicationFiled: October 18, 2012Publication date: April 24, 2014Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Martin STANDING, Milko PAOLUCCI
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Publication number: 20130140673Abstract: A semiconductor device and method are disclosed. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side. Contact areas of the first n-type channel FET and the second n-type channel FET are electrically separated from each other.Type: ApplicationFiled: June 4, 2012Publication date: June 6, 2013Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Oliver Haeberlen, Walter Rieger, Martin Vielemeyer, Lutz Goergens, Martin Poelzl, Milko Paolucci, Johannes Schoiswohl, Joachim Krumrey
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Patent number: 8193559Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side of the semiconductor die, respectively. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side of the semiconductor die opposite to the first side, respectively. The contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other, respectively.Type: GrantFiled: April 7, 2011Date of Patent: June 5, 2012Assignee: Infineon Technologies Austria AGInventors: Oliver Haeberlen, Walter Rieger, Martin Vielemeyer, Lutz Goergens, Martin Poelzl, Milko Paolucci, Johannes Schoiswohl, Joachim Krumrey, Sonja Krumrey, legal representative
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Publication number: 20110241170Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side of the semiconductor die, respectively. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side of the semiconductor die opposite to the first side, respectively. The contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other, respectively.Type: ApplicationFiled: April 7, 2011Publication date: October 6, 2011Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Oliver Haeberlen, Walter Rieger, Martin Vielemeyer, Lutz Goergens, Martin Poelzl, Milko Paolucci, Johannes Schoiswohl, Joachim Krumrey, Sonja Krumrey