Patents by Inventor Mill-Jer Wang

Mill-Jer Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250062202
    Abstract: A semiconductor die and methods of forming the same and a package structure are provided. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads over the semiconductor substrate, a passivation layer over the semiconductor substrate and partially covering the plurality of conductive pads, an interconnecting line disposed on the passivation layer, and a plurality of connectors disposed on and electrically connected to the plurality of conductive pads. Each of the plurality of connectors includes a stacked structure of a first conductive pillar and a second conductive pillar disposed directly on the first conductive pillar, wherein a span of the second conductive pillar is smaller than a span of the first conductive pillar, and an orthogonal projection of the second conductive pillar falls within an orthogonal projection of the first conductive pillar, and the interconnecting line is located beside and spaced apart from the plurality of connectors.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yi Sung, Ta-Hsuan Lin, Hua-Wei Tseng, Mill-Jer Wang
  • Publication number: 20240413012
    Abstract: An embodiment is a method including a first dielectric layer over a first substrate, the first dielectric layer having a first metallization pattern therein. The method also includes forming a second dielectric layer over the first dielectric layer and the first metallization pattern. The method also includes forming a sacrificial pad over and extending into the second dielectric layer, the sacrificial pad being electrically coupled to a first conductive feature in the first metallization pattern. The method also includes performing a circuit probe test on the sacrificial pad. The method also includes after performing the circuit probe test, performing an etch process, the etch process removing the sacrificial pad.
    Type: Application
    Filed: August 16, 2023
    Publication date: December 12, 2024
    Inventors: Tzuan-Horng Liu, An-Jhih Su, Mill-Jer Wang
  • Publication number: 20240377446
    Abstract: A testing device for testing an antenna is provided. The testing device includes a housing, an antenna module for holding the antenna and disposed under the housing, and a receiving module disposed on the housing. The receiving module includes a substrate, a coupling radiation element disposed on the substrate, and a support disposed on the substrate. The coupling radiation element includes a coupling portion and a first branch connecting to the coupling portion.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Chi-Chang LAI, Kai-Yi TANG, Mill-Jer WANG
  • Patent number: 12105131
    Abstract: A testing device for testing an antenna is provided. The testing device includes a housing, an antenna module for holding the antenna and disposed under the housing, and a receiving module disposed on the housing. The antenna module includes a base and a flexible film disposed on the base. The receiving module includes a substrate, a coupling radiation element disposed on the substrate and a support disposed on the substrate and having an opening. The antenna is partially exposed from the opening.
    Type: Grant
    Filed: June 22, 2023
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Chang Lai, Kai-Yi Tang, Mill-Jer Wang
  • Publication number: 20240302410
    Abstract: A probe head structure is provided. The probe head structure includes a flexible substrate having a top surface and a bottom surface. The probe head structure includes a first probe pillar passing through the flexible substrate. The probe head structure includes a redistribution structure on the top surface of the flexible substrate and the first probe pillar. The probe head structure includes a wiring substrate over the redistribution structure. The probe head structure includes a first conductive bump connected between the wiring substrate and the redistribution structure.
    Type: Application
    Filed: May 21, 2024
    Publication date: September 12, 2024
    Inventors: Wen-Yi LIN, Hao CHEN, Chuan-Hsiang SUN, Mill-Jer WANG, Chien-Chen LI, Chen-Shien CHEN
  • Patent number: 12062586
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and multiple first conductive lines over the semiconductor substrate. The first conductive lines are not electrically connected to each other. The semiconductor device structure also includes multiple first magnetic structures wrapped around portions of the first conductive lines and multiple second conductive lines over the semiconductor substrate. The second conductive lines are electrically connected in series. The semiconductor device structure further includes multiple second magnetic structures wrapped around portions of the second conductive lines. A size of each of the second magnetic structures and a size of each of the first magnetic structures are substantially the same.
    Type: Grant
    Filed: April 14, 2023
    Date of Patent: August 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mill-Jer Wang, Tang-Jung Chiu, Chi-Chang Lai, Chia-Heng Tsai, Mirng-Ji Lii, Weil Liao
  • Patent number: 12019097
    Abstract: A probe head structure is provided. The probe head structure includes a flexible substrate having a top surface and a bottom surface. The probe head structure includes a first probe pillar passing through the flexible substrate. The first probe pillar has a first protruding portion protruding from the bottom surface. The probe head structure includes a redistribution structure on the top surface of the flexible substrate and the first probe pillar. The redistribution structure is in direct contact with the flexible substrate and the first probe pillar. The redistribution structure includes a dielectric structure and a wiring structure in the dielectric structure. The wiring structure is electrically connected to the first probe pillar. The probe head structure includes a wiring substrate over the redistribution structure. The probe head structure includes a first conductive bump connected between the wiring substrate and the redistribution structure.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Yi Lin, Hao Chen, Chuan-Hsiang Sun, Mill-Jer Wang, Chien-Chen Li, Chen-Shien Chen
  • Publication number: 20240133942
    Abstract: A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao Chen, Mill-Jer Wang
  • Publication number: 20240088124
    Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: HSIANG-TAI LU, SHUO-MAO CHEN, MILL-JER WANG, FENG-CHENG HSU, CHAO-HSIANG YANG, SHIN-PUU JENG, CHENG-YI HONG, CHIH-HSIEN LIN, DAI-JANG CHEN, CHEN-HUA LIN
  • Patent number: 11906573
    Abstract: A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao Chen, Mill-Jer Wang
  • Publication number: 20240027514
    Abstract: A method includes: providing a first semiconductor device including a backside interconnection structure, the first semiconductor device being formed by a semiconductor process; and generating a physical failure analysis model by an inspection process. The inspection process includes: directing an electron beam toward the frontside of the first semiconductor device; and applying an electrical signal to an electrical contact of the first semiconductor device through an electrical path that goes through a shunt board attached to a switchable interface trace bank, the electrical contact being associated with a position of the electron beam. The method further includes: generating a parameter of a revised semiconductor process according to the physical failure analysis model and the semiconductor process; and forming a second semiconductor device by the revised semiconductor process using the parameter.
    Type: Application
    Filed: February 13, 2023
    Publication date: January 25, 2024
    Inventors: Chia-Hong Lin, Yu-Ting Lin, Mill-Jer Wang
  • Patent number: 11852672
    Abstract: A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTORMANUFACTURING COMPANY LIMITED
    Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Chuan-Ching Wang, Hao Chen
  • Patent number: 11855066
    Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsiang-Tai Lu, Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng, Cheng-Yi Hong, Chih-Hsien Lin, Dai-Jang Chen, Chen-Hua Lin
  • Publication number: 20230333150
    Abstract: A testing device for testing an antenna is provided. The testing device includes a housing, an antenna module for holding the antenna and disposed under the housing, and a receiving module disposed on the housing. The antenna module includes a base and a flexible film disposed on the base. The receiving module includes a substrate, a coupling radiation element disposed on the substrate and a support disposed on the substrate and having an opening. The antenna is partially exposed from the opening.
    Type: Application
    Filed: June 22, 2023
    Publication date: October 19, 2023
    Inventors: Chi-Chang LAI, Kai-Yi TANG, Mill-Jer WANG
  • Patent number: 11726122
    Abstract: A testing device for testing an antenna is provided. The testing device includes a housing, an antenna module, and a receiving module. The antenna module is used for holding the antenna and disposed on the housing, wherein the antenna is coupled to an antenna testing apparatus. The receiving module is disposed on the housing and includes a coupling radiation element physically separated from the antenna, wherein the receiving module is configured to receive an excited signal emitted from the antenna.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Chang Lai, Kai-Yi Tang, Mill-Jer Wang
  • Patent number: 11726112
    Abstract: A circuit probe includes a shielding probe having a base and a conductive probe ring on the base. A shielding cage is attached to the conductive probe ring and has an interior. The shielding cage is configured to be positioned to contain in the interior of the shielding cage at least one integrated circuit formed on a wafer, and to provide electromagnetic shielding of the at least one integrated circuit during testing of the at least one integrated circuit.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Nen Peng, Hsien-Tang Wang, Mill-Jer Wang, Chi-Chang Lai
  • Publication number: 20230253273
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and multiple first conductive lines over the semiconductor substrate. The first conductive lines are not electrically connected to each other. The semiconductor device structure also includes multiple first magnetic structures wrapped around portions of the first conductive lines and multiple second conductive lines over the semiconductor substrate. The second conductive lines are electrically connected in series. The semiconductor device structure further includes multiple second magnetic structures wrapped around portions of the second conductive lines. A size of each of the second magnetic structures and a size of each of the first magnetic structures are substantially the same.
    Type: Application
    Filed: April 14, 2023
    Publication date: August 10, 2023
    Inventors: Mill-Jer WANG, Tang-Jung CHIU, Chi-Chang LAI, Chia-Heng TSAI, Mirng-Ji LII, Weii LIAO
  • Patent number: 11693045
    Abstract: A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: July 4, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao Chen, Mill-Jer Wang
  • Publication number: 20230168296
    Abstract: A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.
    Type: Application
    Filed: January 30, 2023
    Publication date: June 1, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao Chen, Mill-Jer Wang
  • Patent number: 11631621
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first magnetic element and a second magnetic element over the semiconductor substrate. The semiconductor device structure also includes a first conductive line extending exceeding an edge of the first magnetic element. The semiconductor device structure further includes a second conductive line extending exceeding an edge of the second magnetic element. The second conductive line is electrically connected to the first conductive line.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: April 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mill-Jer Wang, Tang-Jung Chiu, Chi-Chang Lai, Chia-Heng Tsai, Mirng-Ji Lii, Weii Liao