Abstract: A pulsed circuit topology to perform a memory array write operation. A write enable pulse width control circuit is responsive to a pulsed clock signal to generate a pulsed write enable signal and a write data path circuit is provided to output a write data signal. The write enable pulse width control circuit and the write data path circuit together control a write operation to a memory cell.

Abstract: A reset first latching mechanism comprises a pulse chopper circuit responsive to a pulsed signal to control initiation and termination of a reset pulse wherein a domino node is to be precharged in response to the reset pulse. The reset first latching mechanism also includes domino logic circuit responsive to an evaluate pulse at an input to evaluate at the domino node based on a logic function performed by the domino logic circuit. The reset pulse is timed such that the reset pulse is completed before the evaluate at the domino node occurs.

Abstract: A global clock self-timed circuit initiates a precharge pulse in response to which a domino node is precharged. A self-terminating precharge circuit coupled to the global clock self-timed circuit and the domino node terminates the precharge pulse after the domino node has been precharged.

Abstract: A pulsed circuit topology including a pulsed domino flip-flop. A circuit includes a domino logic gate having a domino output node responsive to input data during an evaluate pulse. Reset circuitry initiates and self-terminates a reset pulse during which the domino output node is precharged. A latch responsive to a first pulsed clock input signal is provided to latch data indicated at the domino output node.

Abstract: A method is provided for precharging a node in an integrated circuit in which the node is precharged a first predetermined delay after the node evaluates and, thereafter, the precharge ceases after a second shorter predetermined delay.

Abstract: A variable width pulse generator. The pulse generator includes a pulse circuit responsive to a reset signal to provide a pulse circuit signal. A variable delay reset loop path, coupled to the pulse circuit, is responsive to the pulse circuit signal to provide the reset signal. A control signal may vary the width of a pulse generated by the circuit by varying the length of a delay associated with the reset loop path. Both a coarse control signal, such as a signal that selectively removes a logic element in the reset loop path, and a fine control signal, such as a signal that controls a tunable delay element in the reset loop path, may be used to adjust the pulse width.