Patents by Inventor Milos Ivkovic

Milos Ivkovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10849546
    Abstract: Discussed herein is a parametric model for DTI MD histogram fitting, named the Generalized Voss-Dyke function, which is highly successful in segregating NPH cases from potential confounders without reliance on operator dependent region-of-interest analyses or inter-subject registration. The Generalized Voss-Dyke function is useful for managing the imaging of any tissue interfaces.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: December 1, 2020
    Assignee: CORNELL UNIVERSITY
    Inventors: Milos Ivkovic, Norman Relkin, Henning U. Voss, Jonathan P. Dyke
  • Publication number: 20160270710
    Abstract: Discussed herein is a parametric model for DTI MD histogram fitting, named the Generalized Voss-Dyke function, which is highly successful in segregating NPH cases from potential confounders without reliance on operator dependent region-of-interest analyses or inter-subject registration. The Generalized Voss-Dyke function is useful for managing the imaging of any tissue interfaces.
    Type: Application
    Filed: November 11, 2014
    Publication date: September 22, 2016
    Inventors: Milos Ivkovic, Norman Relkin, Henning U. Voss, Jonathan P. Dyke
  • Patent number: 9378835
    Abstract: Methods and apparatus are provided for soft data generation for memory devices using reference cells. At least one soft data value is generated in a memory device by writing a known data to one or more reference cells; reading one or more of the reference cells; obtaining a read statistic based on the read one or more reference cells; and obtaining the at least one soft data value based on the obtained read statistic. The read statistics can optionally be obtained for one or more desired locations of a memory array; or for a given pattern, PATT, in one or more aggressor cells. The read statistic can optionally comprise asymmetric statistics obtained for a plurality of possible values.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: June 28, 2016
    Assignee: Seagate Technology LLC
    Inventors: Harley F. Burger, Jr., Erich F. Haratsch, Milos Ivkovic, Victor Krachkovsky, Nenad Miladinovic, Andrei Vityaev, Johnson Yen
  • Patent number: 9135999
    Abstract: Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: September 15, 2015
    Assignee: Seagate Technology LLC
    Inventors: Harley F. Burger, Erich F. Haratsch, Milos Ivkovic, Victor Krachkovsky, Andrei Vityaev, Clifton Williamson, Johnson Yen
  • Patent number: 9058879
    Abstract: Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: June 16, 2015
    Assignee: Seagate Technology LLC
    Inventors: Harley F. Burger, Erich F. Haratsch, Milos Ivkovic, Victor Krachkovsky, Andrei Vityaev, Clifton Williamson, Johnson Yen
  • Patent number: 9007828
    Abstract: Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: April 14, 2015
    Assignee: LSI Corporation
    Inventors: Harley F. Burger, Erich F. Haratsch, Milos Ivkovic, Victor Krachkovsky, Andrei Vityaev, Clifton Williamson, Johnson Yen
  • Patent number: 8892966
    Abstract: Methods and apparatus for soft data generation for memory devices using decoder performance feedback. At least one soft data value is generated in a memory device, by obtaining performance feedback from a decoder; obtaining an error statistic based on the performance feedback; and generating the at least one soft data value based on the obtained error statistic. The performance feedback comprises one or more of decoded bits, a number of erroneous bits based on data decoded by the decoder and a number of unsatisfied parity checks.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: November 18, 2014
    Assignee: LSI Corporation
    Inventors: Erich F. Haratsch, Milos Ivkovic, Victor Krachkovsky, Nenad Miladinovic, Andrei Vityaev, Clifton Williamson, Johnson Yen
  • Patent number: 8830748
    Abstract: Methods and apparatus are provided for soft data generation for memory devices. At least one soft data value is generated for a memory device, by obtaining at least one hard read value; and generating the soft data value associated with the at least one hard read value based on statistics for reading the hard read value. The hard read value may be one or more of data bits, voltage levels, current levels and resistance levels. The generated soft data value may be one or more of (i) a soft read value that is used to generate one or more log likelihood ratios, and (ii) one or more log likelihood ratios. The statistics comprise one or more of bit-based statistics and cell-based statistics. The statistics may also optionally comprise pattern-dependent disturbance of at least one aggressor cell on the target cell, as well as location-specific statistics.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: September 9, 2014
    Assignee: LSI Corporation
    Inventors: Erich F. Haratsch, Milos Ivkovic, Victor Krachkovsky, Nenad Miladinovic, Andrei Vityaev, Clifton Williamson, Johnson Yen
  • Patent number: 8797795
    Abstract: Methods and apparatus are provided for intercell interference mitigation using modulation coding. During programming of a flash memory, a modulation encoding is performed that selects one or more levels for programming the flash memory such that a reduced number of cells in the flash memory are programmed with a value that violates one or more predefined criteria. During a reading of a flash memory, a modulation decoding is performed that assigns one or more levels to cells in the flash memory such that a reduced number of cells in the flash memory are read with a value that violates one or more predefined criteria. The predefined criteria can be based, for example, on one or more of an amount of disturbance caused by the programmed cell; a voltage shift of a programmed cell: a voltage stored by a programmed cell; an amount of change in current through a programmed cell; and an amount of current through a programmed cell.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: August 5, 2014
    Assignee: LSI Corporation
    Inventors: Nils Graef, Erich F. Haratsch, Milos Ivkovic, Victor Krachkovsky, Andrei Vityaev, Johnson Yen
  • Patent number: 8788923
    Abstract: Methods and apparatus are provided for soft demapping and intercell interference mitigation in flash memories. In one variation, a target cell in a flash memory device capable of storing at least two data levels, s, per cell is read by obtaining a measured read value, r, for at least one target cell in the flash memory; obtaining a value, h, representing data stored for at least one aggressor cell in the flash memory; selecting one or more probability density functions based on a pattern of values stored in at least a portion of the flash memory, wherein the probability density functions comprises pattern-dependent disturbance of one or more aggressor cells on the at least one target cell in the flash memory; evaluating at least one selected probability density function based on the measured read value, r; and computing one or more log likelihood ratios based on a result of the evaluating step.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: July 22, 2014
    Assignee: LSI Corporation
    Inventors: Erich F. Haratsch, Milos Ivkovic, Victor Krachkovsky, Nenad Miladinovic, Andrei Vityaev, Johnson Yen
  • Patent number: 8724381
    Abstract: Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: May 13, 2014
    Assignee: Agere Systems LLC
    Inventors: Harley F. Burger, Jr., Erich F. Haratsch, Milos Ivkovic, Victor Krachkovsky, Andrei Vityaev, Clifton Williamson, Johnson Yen
  • Publication number: 20140126288
    Abstract: Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 8, 2014
    Applicant: Agere Systems LLC
    Inventors: Harley F. Burger, Erich F. Haratsch, Milos Ivkovic, Victor Krachkovsky, Andrei Vityaev, Clifton Williamson, Johnson Yen
  • Publication number: 20140126287
    Abstract: Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 8, 2014
    Applicant: Agere Systems LLC
    Inventors: Harley F. Burger, Erich F. Haratsch, Milos Ivkovic, Victor Krachkovsky, Andrei Vityaev, Clifton Williamson, Johnson Yen
  • Patent number: 8667039
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a noise predictive filter circuit, a scaling factor adaptation circuit, and a scaling factor application circuit. The noise predictive filter circuit is operable to perform a noise predictive filtering process on a data input based on a filter tap to yield a noise filtered output. The scaling factor adaptation circuit is operable to calculate a scaling factor based at least in part on a derivative of the noise filtered output. The scaling factor application circuit is operable to apply the scaling factor to scale the noise filtered output.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: March 4, 2014
    Assignee: LSI Corporation
    Inventors: Milos Ivkovic, Shaohua Yang
  • Patent number: 8661311
    Abstract: Various embodiments of the present invention provide systems and methods for data processing using variable scaling.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: February 25, 2014
    Assignee: LSI Corporation
    Inventors: Shaohua Yang, Milos Ivkovic
  • Patent number: 8634250
    Abstract: Methods and apparatus are provided for programming multiple program values per signal level in flash memories. A flash memory device having a plurality of program values is programmed by programming the flash memory device for a given signal level, wherein the programming step comprises a programming phase and a plurality of verify phases. In another variation, a flash memory device having a plurality of program values is programmed, and the programming step comprises a programming phase and a plurality of verify phases, wherein at least one signal level comprises a plurality of the program values. The signal levels or the program values (or both) can be represented using one or more of a voltage, a current and a resistance.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: January 21, 2014
    Assignee: LSI Corporation
    Inventors: Erich F. Haratsch, Milos Ivkovic, Victor Krachkovsky, Nenad Miladinovic, Andrei Vityaev, Johnson Yen
  • Patent number: 8526230
    Abstract: Methods and apparatus are provided for write-side intercell interference mitigation in flash memories. A flash memory device is written by obtaining program data to be written to at least one target cell in the flash memory; obtaining one or more bits of program data for at least one aggressor cell to be programmed later than the target cell: and precompensating for intercell interference for the target cell by generating precompensated program values. The aggressor cells comprise one or more cells adjacent to the target cell, such as adjacent cells in a same wordline as the target cell and/or cells in an upper or lower adjacent wordline to the target cell. The precompensated program values for the target cell are optionally provided to the flash memory.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: September 3, 2013
    Assignee: LSI Corporation
    Inventors: Erich F. Haratsch, Milos Ivkovic, Victor Krachkovsky, Nenad Miladinovic, Andrei Vityaev, Johnson Yen
  • Patent number: 8462549
    Abstract: Methods and apparatus are provided for read-side intercell interference mitigation in flash memories. A flash memory device is read by obtaining a read value for at least one target cell; obtaining a value representing a voltage stored in at least one aggressor cell that was programmed after the target cell; determining intercell interference for the target cell from the at least one aggressor cell; and obtaining a new read value that compensates for the intercell interference by removing the determined intercell interference from the read value for the at least one target cell. The new read value can optionally be provided to a decoder. In an iterative implementation, one or more intercell interference mitigation parameters can be adjusted if a decoding error occurs.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: June 11, 2013
    Assignee: LSI Corporation
    Inventors: Erich F. Haratsch, Milos Ivkovic, Victor Krachkovsky, Nenad Miladinovic, Andrei Vityaev, Johnson Yen
  • Patent number: 8418019
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a decoder circuit and a scalar circuit. The decoder circuit is operable to perform a data decoding algorithm by processing at least one decoder message, and the scalar circuit is operable to multiply the decoder message by a variable scalar value.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: April 9, 2013
    Assignee: LSI Corporation
    Inventors: Milos Ivkovic, Shaohua Yang
  • Publication number: 20120124118
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a noise predictive filter circuit, a scaling factor adaptation circuit, and a scaling factor application circuit. The noise predictive filter circuit is operable to perform a noise predictive filtering process on a data input based on a filter tap to yield a noise filtered output. The scaling factor adaptation circuit is operable to calculate a scaling factor based at least in part on a derivative of the noise filtered output. The scaling factor application circuit is operable to apply the scaling factor to scale the noise filtered output.
    Type: Application
    Filed: November 17, 2010
    Publication date: May 17, 2012
    Inventors: Milos Ivkovic, Shaohua Yang