Patents by Inventor Milova PAUL
Milova PAUL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11942472Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a vertical silicon-controlled rectifier (SCR) connecting to an anode, and includes a buried layer of a first dopant type in electrical contact with an underlying buried layer a second dopant type split with an isolation region of the first dopant type within a substrate.Type: GrantFiled: September 15, 2021Date of Patent: March 26, 2024Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Kyong Jin Hwang, Milova Paul, Sagar Premnath Karalkar, Robert J. Gauthier, Jr.
-
Patent number: 11824125Abstract: An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a substrate, an active region, a first terminal region, and a second terminal region. The substrate includes dopants having a first dopant conductivity. The active region is arranged over the substrate and has an upper surface. The first terminal region and the second terminal region are arranged in the active region laterally spaced apart from each other. The first terminal region and the second terminal region each include a well region having dopants of the first dopant conductivity and a first doped region arranged in the well region. The first doped region includes dopants having a second dopant conductivity.Type: GrantFiled: October 27, 2021Date of Patent: November 21, 2023Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Sagar Premnath Karalkar, James Jerry Joseph, Jie Zeng, Milova Paul, Kyong Jin Hwang
-
Patent number: 11776952Abstract: Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure includes first and second wells in the semiconductor substrate, a first terminal including a first doped region in the first well, and a second terminal including a second doped region in the second well. The first well and the second doped region have a first conductivity type, and the second well and the first doped region have a second conductivity type opposite to the first conductivity type. First and second conductor layers are positioned on the semiconductor substrate. The first conductor layer partially overlaps with the first well, and the second conductor layer partially overlaps with the second well. A third doped region, which has the second conductivity type, is laterally positioned in the semiconductor substrate between the first and second conductor layers.Type: GrantFiled: May 5, 2022Date of Patent: October 3, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Sagar Premnath Karalkar, Jie Zeng, Milova Paul, Souvick Mitra
-
Publication number: 20230141491Abstract: Disclosed is a semiconductor structure including a semiconductor substrate (e.g., a P-substrate) and a symmetric BDSCR. The BDSCR includes, within the substrate, a first well (e.g., a low-doped deep Nwell) and, within the first well, symmetric side sections and a middle section positioned laterally between the side sections. Each side section includes: second and third wells (e.g., Pwells), where the third well is shallower than and has a higher conductivity level than the second well. Each middle section includes multiple floating wells including: two fourth wells (e.g., Nwells), which have a higher conductivity level than the first well, and a fifth well (e.g., another Pwell), which is positioned laterally between and shallower than the fourth wells. By incorporating the floating wells into the middle section, high current tolerance is improved.Type: ApplicationFiled: November 11, 2021Publication date: May 11, 2023Applicant: GlobalFoundries U.S. Inc.Inventors: Sagar Premnath Karalkar, Prantik Mahajan, Jie Zeng, Ajay Ajay, Milova Paul, Souvick Mitra
-
Publication number: 20230130632Abstract: An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a substrate, an active region, a first terminal region, and a second terminal region. The substrate includes dopants having a first dopant conductivity. The active region is arranged over the substrate and has an upper surface. The first terminal region and the second terminal region are arranged in the active region laterally spaced apart from each other. The first terminal region and the second terminal region each include a well region having dopants of the first dopant conductivity and a first doped region arranged in the well region. The first doped region includes dopants having a second dopant conductivity.Type: ApplicationFiled: October 27, 2021Publication date: April 27, 2023Inventors: SAGAR PREMNATH KARALKAR, JAMES JERRY JOSEPH, JIE ZENG, MILOVA PAUL, KYONG JIN HWANG
-
Patent number: 11626512Abstract: An ESD protection device may include a substrate having first and second substrate layers, and first and second bridged regions. Each substrate layer may include first and second border regions and a middle region laterally therebetween. Each bridged region may be arranged within the middle region and a respective border region of the second substrate layer. The middle region of the second substrate layer may be laterally narrower than the middle region of the first substrate layer. Each border region of the second substrate layer may be partially arranged over the middle region of the first substrate layer and partially arranged over a respective border region of the first substrate layer. The border regions of the substrate layers, and the bridged regions may have a first conductivity type, and the middle regions of the substrate layers may have a second conductivity type different from the first conductivity type.Type: GrantFiled: January 15, 2021Date of Patent: April 11, 2023Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Jie Zeng, Milova Paul, Sagar Premnath Karalkar
-
Publication number: 20230078157Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture.Type: ApplicationFiled: September 15, 2021Publication date: March 16, 2023Inventors: Kyong Jin HWANG, Milova PAUL, Sagar Premnath Karalkar, Robert J. Gauthier, JR.
-
Publication number: 20230039286Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure comprising a vertical silicon controlled rectifier (SCR) connecting to an anode, and comprising a buried layer of a first dopant type in electrical contact with an underlying continuous layer of a second dopant type within a substrate.Type: ApplicationFiled: August 5, 2021Publication date: February 9, 2023Inventors: Kyong Jin HWANG, Milova PAUL, Sagar P. Karalkar, Robert J. Gauthier, Jr.
-
Publication number: 20220231151Abstract: An ESD protection device may include a substrate having first and second substrate layers, and first and second bridged regions. Each substrate layer may include first and second border regions and a middle region laterally therebetween. Each bridged region may be arranged within the middle region and a respective border region of the second substrate layer. The middle region of the second substrate layer may be laterally narrower than the middle region of the first substrate layer. Each border region of the second substrate layer may be partially arranged over the middle region of the first substrate layer and partially arranged over a respective border region of the first substrate layer. The border regions of the substrate layers, and the bridged regions may have a first conductivity type, and the middle regions of the substrate layers may have a second conductivity type different from the first conductivity type.Type: ApplicationFiled: January 15, 2021Publication date: July 21, 2022Inventors: Jie ZENG, Milova PAUL, Sagar Premnath KARALKAR
-
Patent number: 10629586Abstract: The present disclosure relates to a Dual Fin SCR device having two parallel fins on which cathode, anode, n- and p-type triggering taps are selectively doped, wherein one Fin (or group of parallel Fins) comprises anode and n-tap, and other Fin (or group of parallel Fins) comprises cathode and p-tap. As key regions of the proposed SCR (anode and cathode), which carry majority of current after triggering, are placed diagonally, they provide substantial benefit in terms of spreading current and dissipating heat. The proposed SCR ESD protection device helps obtain regenerative feedback between base-collector junctions of two back-to-back bipolar transistors, which enables the proposed SCR to shunt ESD current. The proposed SCR design enables lower trigger and holding voltage for efficient and robust ESD protection. The proposed SCR device/design helps offer a tunable trigger voltage and a holding voltage with highfailure threshold.Type: GrantFiled: January 30, 2018Date of Patent: April 21, 2020Assignee: INDIAN INSTITUTE OF SCIENCEInventors: Milova Paul, Mayank Shrivastava, B. Sampath Kumar, Christian Russ, Harald Gossner
-
Patent number: 10535762Abstract: SCRs are a must for ESD protection in low voltage—high speed I/O as well as ESD protection of RF pads due to least parasitic loading and smallest foot print offered by SCRs. However, conventionally designed SCRs in FinFET and Nanowire technology suffer from very high turn-on and holding voltage. This issue becomes more severe in sub-14 nm non-planar technologies and cannot be handled by conventional approaches like diode- or transient-turn-on techniques. Proposed invention discloses SCR concept for FinFET and Nanowire technology with diffused junction profiles with sub-3V trigger and holding voltage for efficient and robust ESD protection. Besides low trigger and holding voltage, the proposed device offers a 3 times better ESD robustness per unit area.Type: GrantFiled: February 19, 2018Date of Patent: January 14, 2020Assignee: INDIAN INSTITUTE OF SCIENCEInventors: Mayank Shrivastava, Milova Paul, Harald Gossner
-
Patent number: 10483258Abstract: The present disclosure relates to non-planar ESD protection devices. The present disclosure provides a device structure and method of fabricating the structure that is essentially immune to latch-up and possess high ESD robustness and reliability. In an aspect, the present disclosure provides a mixed silicidation and selective epitaxy (epi) FinFET processes for latch-up immunity together with ESD robustness, thereby allowing achievement of ESD efficient parasitic structures together with latch-up immune and reliable functional devices. The present disclosure provides a dual silicidation scheme where ESD protection element(s) have fins that are partially silicided, and functional devices have fins that are fully silicided.Type: GrantFiled: February 19, 2018Date of Patent: November 19, 2019Assignee: INDIAN INSTITUTE OF SCIENCEInventors: Mayank Shrivastava, Milova Paul, Harald Gossner
-
Patent number: 10319662Abstract: The present disclosure relates to a thermal management solution for ESD protection devices in advanced Fin- and/or Nanowire-based technology nodes, by employing localized nano heat sinks, which enable heat transport from local hot spots to surface of chip, which allows significant reduction in peak temperature for a given ESD current. In an aspect, the proposed semiconductor device can include at least one fin having a source and a drain disposed over a p-well or a n-well in a substrate; an electrically floating dummy metal gate disposed close to drain or hot spot over at least a portion of the at least one fin, and an electrical metal gate is disposed close to the source; and a nano-heat sink operatively coupled with the dummy metal gate and terminating at the surface of chip in which the semiconductor device is configured so as to enable transfer of heat received from the at least one fin through the dummy metal gate to the surface of the chip.Type: GrantFiled: January 30, 2018Date of Patent: June 11, 2019Assignee: INDIAN INSTITUTE OF SCIENCEInventors: Mayank Shrivastava, Milova Paul, Christian Russ, Harald Gossner
-
Patent number: 10211200Abstract: The present disclosure relates to a Silicon Controlled Rectifier (SCR) in non-planar technology to provide a robust ESD protection in System on Chip employing non-planar technologies. The disclosed SCR incorporates wire or fin shaped nanostructures extending from p-type tap to cathode, from the cathode to anode, and from the anode to n-type tap to provide parallel trigger paths to prevent problem of current crowding at the base emitter junction that limits efficient turn-on in conventional SCRs. The proposed structure helps in offering lower trigger and holding voltage, and therefore very high failure currents. The disclosed SCR has sub-3V trigger and holding voltage to provide an efficient and robust ESD protection in SOCs. The proposed device also offers three times better ESD robustness per unit area. Further the proposed SCR has no added capacitive loading and is compatible with standard process flow and design rules.Type: GrantFiled: January 30, 2018Date of Patent: February 19, 2019Assignee: INDIAN INSTITUTE OF SCIENCEInventors: Mayank Shrivastava, Milova Paul, Christian Russ, Harald Gossner
-
Publication number: 20190013310Abstract: The present disclosure relates to a Dual Fin SCR device having two parallel fins on which cathode, anode, n- and p- type triggering taps are selectively doped, wherein one Fin (or group of parallel Fins) comprises anode and n-tap, and other Fin (or group of parallel Fins) comprises cathode and p-tap. As key regions of the proposed SCR (anode and cathode), which carry majority of current after triggering, are placed diagonally, they provide substantial benefit in terms of spreading current and dissipating heat. The proposed SCR ESD protection device helps obtain regenerative feedback between base—collector junctions of two back-to-back bipolar transistors, which enables the proposed SCR to shunt ESD current. The proposed SCR design enables lower trigger and holding voltage for efficient and robust ESD protection. The proposed SCR device/design helps offer a tunable trigger voltage and a holding voltage with highfailure threshold.Type: ApplicationFiled: January 30, 2018Publication date: January 10, 2019Applicant: INDIAN INSTITUTE OF SCIENCEInventors: Milova PAUL, Mayank SHRIVASTAVA, B. Sampath KUMAR, Christian RUSS, Harald GOSSNER
-
Publication number: 20180247929Abstract: The present disclosure relates to non-planar ESD protection devices. The present disclosure provides a device structure and method of fabricating the structure that is essentially immune to latch-up and possess high ESD robustness and reliability. In an aspect, the present disclosure provides a mixed silicidation and selective epitaxy (epi) FinFET processes for latch-up immunity together with ESD robustness, thereby allowing achievement of ESD efficient parasitic structures together with latch-up immune and reliable functional devices. The present disclosure provides a dual silicidation scheme where ESD protection element(s) have fins that are partially silicided, and functional devices have fins that are fully silicided.Type: ApplicationFiled: February 19, 2018Publication date: August 30, 2018Inventors: Mayank Shrivastava, Milova Paul, Harald Gossner
-
Publication number: 20180248025Abstract: SCRs are a must for ESD protection in low voltage—high speed I/O as well as ESD protection of RF pads due to least parasitic loading and smallest foot print offered by SCRs. However, conventionally designed SCRs in FinFET and Nanowire technology suffer from very high turn-on and holding voltage. This issue becomes more severe in sub-14 nm non-planar technologies and cannot be handled by conventional approaches like diode- or transient-turn-on techniques. Proposed invention discloses SCR concept for FinFET and Nanowire technology with diffused junction profiles with sub-3V trigger and holding voltage for efficient and robust ESD protection. Besides low trigger and holding voltage, the proposed device offers a 3 times better ESD robustness per unit area.Type: ApplicationFiled: February 19, 2018Publication date: August 30, 2018Inventors: Mayank Shrivastava, Milova Paul, Harald Gossner
-
Publication number: 20180226317Abstract: The present disclosure relates to a thermal management solution for ESD protection devices in advanced Fin- and/or Nanowire-based technology nodes, by employing localized nano heat sinks, which enable heat transport from local hot spots to surface of chip, which allows significant reduction in peak temperature for a given ESD current. In an aspect, the proposed semiconductor device can include at least one fin having a source and a drain disposed over a p-well or a n-well in a substrate; an electrically floating dummy metal gate disposed close to drain or hot spot over at least a portion of the at least one fin, and an electrical metal gate is disposed close to the source; and a nano-heat sink operatively coupled with the dummy metal gate and terminating at the surface of chip in which the semiconductor device is configured so as to enable transfer of heat received from the at least one fin through the dummy metal gate to the surface of the chip.Type: ApplicationFiled: January 30, 2018Publication date: August 9, 2018Applicant: INDIAN INSTITUTE OF SCIENCEInventors: Mayank SHRIVASTAVA, Milova PAUL, Christian RUSS, Harald GOSSNER
-
Publication number: 20180219007Abstract: The present disclosure relates to a Silicon Controlled Rectifier (SCR) in non-planar technology to provide a robust ESD protection in System on Chip employing non-planar technologies. The disclosed SCR incorporates wire or fin shaped nanostructures extending from p-type tap to cathode, from the cathode to anode, and from the anode to n-type tap to provide parallel trigger paths to prevent problem of current crowding at the base emitter junction that limits efficient turn-on in conventional SCRs. The proposed structure helps in offering lower trigger and holding voltage, and therefore very high failure currents. The disclosed SCR has sub-3V trigger and holding voltage to provide an efficient and robust ESD protection in SOCs. The proposed device also offers three times better ESD robustness per unit area. Further the proposed SCR has no added capacitive loading and is compatible with standard process flow and design rules.Type: ApplicationFiled: January 30, 2018Publication date: August 2, 2018Applicant: INDIAN INSTITUTE OF SCIENCEInventors: Mayank SHRIVASTAVA, Milova PAUL, Christian RUSS, Harald GOSSNER